Granted Patent
Utility
US 6,618,286
· Confirmation No. 6784
NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE WITH A MEMORY ARRAY PREVENTING GENERATION OF A THROUGH CURRENT PATH
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⬇ PDF
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Code | Description | Pages | ||
|---|---|---|---|---|---|
| 2003-06-30 | IFEE |
Issue Fee Payment (PTO-85B) | 1 | View | |
| 2002-05-16 | TRNA |
Transmittal of New Application | 2 | View | |
| 2002-05-16 | SPEC |
Specification | 20 | View | |
| 2002-05-16 | CLM |
Claims | 4 | View | |
| 2002-05-16 | ABST |
Abstract | 1 | View | |
| 2002-05-16 | DRW |
Drawings-only black and white line drawings | 11 | View | |
| 2002-05-16 | OATH |
Oath or Declaration filed | 3 | View |
Inventors
Hiroshi Kato
Hyogo, JAPAN
Tsukasa Ooishi
Hyogo, JAPAN
Classification
USPC
365/185.11
G11C16/3445
H10B69/00
G11C5/025
G11C8/12
G11C16/0475
Prosecution
- Examiner
- LAM, DAVID
- Art Unit
- 2818
- Docket No.
- 57454-562
- Confirmation No.
- 6784
Foreign Priority
2001-353238(P)
·
2001-11-19
·
JAPAN
Publication
- Pub. No.
- US20030095435A1
- Pub. Date
- 2003-05-22
Patent Term Adjustment
0days
No related applications found.
CHANGE OF ADDRESS
Recorded 2017-11-29
ASSIGNMENT OF ASSIGNOR'S INTEREST
Recorded 2011-03-18
ASSIGNMENT OF ASSIGNOR'S INTEREST
Recorded 2002-05-16
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Quick Facts
- Patent No.
- US 6,618,286
- App. No.
- 10/146,031
- Filed
- 2002-05-16
- Granted
- 2003-09-09
- Pub. No.
- US20030095435A1
- Examiner
- LAM, DAVID
- Art Unit
- 2818
- PTA
- 0 days
External Links