IP Library › Patent Application 10163192
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App. No. 10/163,192 · Confirmation No. 6416

Method and apparatus for evaluating an integrated circuit model

Abandoned -- Failure to Respond to an Office Action View Publication ↗
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 Code Description Pages PDF
2006-07-11 ABN Abandonment 2 View
2005-10-04 CTNF Non-Final Rejection 10 View
2005-10-04 1449 List of References cited by applicant and considered by examiner 3 View
2005-10-04 892 List of references cited by examiner 3 View
2005-10-04 BIB Bibliographic Data Sheet 1 View
2005-10-04 FWCLM Index of Claims 1 View
2005-10-04 SRFW Search information including classification, databases and other search related notes 1 View
2005-09-16 SRNT Examiner's search strategy and results 12 View
2005-09-15 SRNT Examiner's search strategy and results 20 View
2005-03-14 IDS Information Disclosure Statement (IDS) Form (SB08) 8 View
2005-03-14 FOR Foreign Reference 31 View
2002-09-03 LET. Miscellaneous Incoming Letter 4 View
2002-09-03 OATH Oath or Declaration filed 3 View
2002-09-03 IDS Information Disclosure Statement (IDS) Form (SB08) 3 View
2002-07-05 CTMS Miscellaneous Action with shortened statutory period (SSP) 2 View
2002-06-04 TRNA Transmittal of New Application 2 View
2002-06-04 SPEC Specification 19 View
2002-06-04 CLM Claims 5 View
2002-06-04 ABST Abstract 1 View
2002-06-04 DRW Drawings-only black and white line drawings 9 View
2002-06-04 OATH Oath or Declaration filed 4 View
2002-06-04 WFEE Fee Worksheet (SB06) 1 View
2002-06-04 WFEE Fee Worksheet (SB06) 1 View
2002-06-04 WCLM Claims Worksheet (PTO-2022) 1 View
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Quick Facts
App. No.
10/163,192
Filed
2002-06-04
Pub. No.
US20030004699A1
Art Unit
2123