Non-volatile memory and method with reduced source line bias errors
View Patent ↗Source line bias is an error introduced by a non-zero resistance in the ground loop of the read/write circuits. During sensing the control gate voltage of a memory cell is erroneously biased by a voltage drop across the resistance. This error is minimized when the current flowing though the ground loop is reduced. A method for reducing source line bias is accomplished by read/write circuits with features and techniques for multi-pass sensing. When a page of memory cells are being sensed in parallel, each pass helps to identify and shut down the memory cells with conduction current higher than a given demarcation current value. In this way, sensing in subsequent passes will be less affected by source line bias since the total amount of current flow is significantly reduced by eliminating contributions from the higher current cells.
1. In a non-volatile memory device having a plurality of memory cells to be sensed in parallel, each memory cell having a source electrode, and the plurality of memory cells having their source electrodes coupled together into a combined source line, a method of sensing comprising:
(a) providing a predetermined demarcation current value to discriminate between two memory states;
(b) sensing the plurality of memory cells in parallel;
(c) identifying those memory cells having conduction currents higher than said predetermined demarcation current value;
(d) inhibiting the conduction currents of those higher current memory cells;
(e) repeating (b) to (d) for a predetermined number of times; and
(f) sensing the plurality of memory cells in parallel in a final pass.
2. The method of claim 1 , wherein said predetermined number of times is zero.
3. The method of claim 1 , wherein said predetermined number of times is one or greater.
4. The method of claim 1 , wherein:
the conduction currents of said plurality of memory cells are sensed though a plurality of associated bit lines; and
said step of identifying those high current memory cells includes:
precharging said plurality of associated bit lines with a constant current source having a predetermined current limitation;
identifying those memory cells having conduction currents higher than said predetermined demarcation current value by their associated bit lines' precharging rates.
5. The method of claim 1 , wherein:
said sensing is performed by an associated plurality of sense amplifier in parallel; and
said step of identifying those high current memory cells includes:
identifying those memory cells by using their associated sense amplifiers to compare their conduction currents relative to said predetermined demarcation current value.
6. The method of claim 1 , wherein:
the conduction currents of said plurality of memory cells are sensed though a plurality of associated bit lines; and
said inhibiting the conduction currents includes pulling the associated bit lines of those memory cells to ground.
7. The method of claim 1 , wherein:
said plurality of memory cells is non-volatile memory.
8. The method of claim 1 , wherein:
said plurality of memory cells is flash EEPROM.
9. The method as in any one of claims 1 - 8 , wherein:
each memory cell stores one bit of data.
10. The method as in any one of claims 1 - 8 , wherein:
each memory cells stores more than one bit of data.
11. In a non-volatile memory device having a plurality of memory cells to be sensed in parallel, each memory cell having a source electrode, and the plurality of memory cells having their source electrodes coupled together into a combined source line, a read system comprising:
a controller; and
a plurality of sensing circuits for sensing said plurality of memory cells in parallel, each sensing circuit further comprising:
a discriminator coupled to receive a conduction current of an associated memory cell, said discriminator discriminating whether the conduction current is higher or lower than a predetermined demarcation current value;
a latch being set to register the associated memory cell in response to said discriminator identifying a conduction current higher than said predetermined demarcation current value; and
an inhibitor being enabled by said latch being set to turn off the conduction current of the associated memory cell; and wherein
said controller controls said plurality of sensing circuits to operate a predetermined number of times before reading out the determined memory state.
12. The read circuit as in claim 11 , wherein said predetermined number of times is two.
13. The read circuit as in claim 11 , wherein said predetermined number of times is greater than two.
14. The read circuit as in claim 11 , further comprising:
a precharge circuit which is a constant current source having a predetermined current limitation; and wherein:
the conduction currents of said plurality of memory cells are sensed though a plurality of associated bit lines;
said precharge circuit precharging said plurality of associated bit lines; and
said plurality of sensing circuits identifying those memory cells having conduction currents higher than said predetermined demarcation current value by their associated bit lines' precharging rates.
15. The read circuit as in claim 11 , wherein:
said plurality of sensing circuits identifying those memory cells having conduction currents by comparing their conduction currents relative to said predetermined demarcation current value.
16. The read circuit as in claim 11 , wherein:
the conduction currents of said plurality of memory cells are sensed though a plurality of associated bit lines; and
said inhibitor turns off the conduction currents by pulling the associated bit lines of those memory cells to ground.
17. The read circuit as in claim 11 , wherein:
said plurality of memory cells is non-volatile memory.
18. The read circuit as in claim 11 , wherein:
said plurality of memory cells is flash EEPROM.
19. The read circuit as in any one of claims 11 - 18 , wherein:
each memory cell stores one bit of data.
20. The read circuit as in any one of claims 11 - 18 , wherein:
each memory cell stores more than one bit of data.
21. In a non-volatile memory device having a plurality of memory cells to be sensed in parallel, each memory cell having a source electrode, and the plurality of memory cells having their source electrodes coupled together into a combined source line, a read system comprising:
a controlling means; and
a plurality of sensing circuits for sensing conduction currents of said plurality of memory cells in parallel, each sensing circuit further comprising:
means for discriminating whether the conduction current is higher or lower than a predetermined demarcation current value;
means for registering the associated memory cell in response whenever its conduction current is identified to be higher than said predetermined demarcation current value; and
means for inhibiting the associated memory cell with said higher conduction current; and wherein
said controlling means operating said plurality of sensing circuits a predetermined number of times before reading out the sensed memory state in a final pass.
22. The read circuit as in claim 21 , wherein said predetermined number of times is two.
23. The read circuit as in claim 21 , wherein said predetermined number of times is greater than two.
24. The read circuit as in claim 21 , further comprising:
a precharge circuit which is a constant current source having a predetermined current limitation; and wherein:
the conduction currents of said plurality of memory cells are sensed though a plurality of associated bit lines;
said precharge circuit precharging said plurality of associated bit lines; and
said plurality of sensing circuits identifying those memory cells having conduction currents higher than said predetermined demarcation current value by their associated bit lines' precharging rates.
25. The read circuit as in claim 21 , wherein:
said plurality of sensing circuits identifying those memory cells having conduction currents by comparing their conduction currents relative to said predetermined demarcation current value.
26. The read circuit as in claim 21 , wherein:
the conduction currents of said plurality of memory cells are sensed though a plurality of associated bit lines; and
said inhibiting means turns off the conduction currents by pulling the associated bit lines of those memory cells to ground.
27. The read circuit as in claim 21 , wherein:
said plurality of memory cells is non-volatile memory.
28. The read circuit as in claim 21 , wherein:
said plurality of memory cells is flash EEPROM.
29. The read circuit as in any one of claims 21 - 28 , wherein:
each memory cell stores one bit of data.
30. The read circuit as in any one of claims 21 - 28 , wherein:
each memory cell stores more than one bit of data.