Granted Patent
Utility
US 6,584,005
· Confirmation No. 1864
SEMICONDUCTOR MEMORY DEVICE PREVENTING ERRONEOUS WRITING IN WRITE OPERATION AND DELAY IN READ OPERATION
Patented Case
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Code | Description | Pages | ||
|---|---|---|---|---|---|
| 2002-11-25 | TRNA |
Transmittal of New Application | 2 | View | |
| 2002-11-25 | SPEC |
Specification | 38 | View | |
| 2002-11-25 | CLM |
Claims | 5 | View | |
| 2002-11-25 | ABST |
Abstract | 1 | View | |
| 2002-11-25 | DRW |
Drawings-only black and white line drawings | 25 | View | |
| 2002-11-25 | OATH |
Oath or Declaration filed | 4 | View |
Inventors
Hiroshi Kato
Hyogo, JAPAN
Masatoshi Ishikawa
Hyogo, JAPAN
Tsukasa Ooishi
Hyogo, JAPAN
Jun Ohtani
Hyogo, JAPAN
Hideto Hidaka
Hyogo, JAPAN
Attorneys & Agents of Record
Classification
USPC
365/63
G11C16/24
G11C7/12
G11C16/0475
G11C16/0491
G11C16/08
Prosecution
- Examiner
- NGUYEN, TUAN T
- Art Unit
- 2824
- Docket No.
- 57454-800
- Confirmation No.
- 1864
Foreign Priority
2002-151352(P)
·
2002-05-24
·
JAPAN
Patent Term Adjustment
0days
No related applications found.
CHANGE OF ADDRESS
Recorded 2017-11-29
ASSIGNMENT OF ASSIGNOR'S INTEREST
Recorded 2011-03-18
ASSIGNMENT OF ASSIGNOR'S INTEREST
Recorded 2002-11-25
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Quick Facts
- Patent No.
- US 6,584,005
- App. No.
- 10/302,963
- Filed
- 2002-11-25
- Granted
- 2003-06-24
- Examiner
- NGUYEN, TUAN T
- Art Unit
- 2824
- PTA
- 0 days
External Links