Random-access memory devices comprising a dioded buffer

1. Random-access memory device comprising n select lines, m bit lines, n×m RAM cells, each RAM cell being connected to a corresponding one of said n select lines and to a corresponding one of said m bit lines, and k select buffers for selecting the read-out of one out of the n select lines when receiving a selection signal, where k smaller or equal than n, wherein

each of said select buffers comprises an inverter serving as driver, the inverter being followed by a diode for limiting output voltage swings at the respective select line

whereby the select buffers provide a certain voltage to the select lines that is smaller than a supply voltage of the device.

2. The Random-access memory device of claim 1 , whereby each RAM cell comprises a select transistor situated between one of said m bit lines and one of said n select lines.

3. The Random-access memory device of claim 2 , whereby the select transistors are driven with a voltage that ensures a working mode of the select transistors in weak, inversion.

4. The Random-access memory device of claim 2 , whereby the select transistors are driven with a voltage so as to operate them as high-ohmic switches.

5. The Random-access memory device of claim 2 , whereby the select buffers ensure that a certain voltage is provided at the respective select line, this certain voltage being smaller than the random-access memory device's supply voltage and larger than a threshold voltage of the select transistors.

6. The Random-access memory device of claim 5 , whereby the supply voltage is between 1.5 V and 3.3 V and the certain voltage is between 0.5 V and 1 V, and preferably between 0.7 V and 0.9 V.

7. The Random-access memory device of claim 1 , whereby the select buffers are provided for selecting several of the n×m RAM cells through the select line to which the respective select buffer is connected for the read out of data.

8. The Randomaccess memory device of claim 1 , whereby a transistor branched as diode serves as the diode for limiting output voltage swings.

9. Display, comprising a random-access memory device according to claim 1 .

10. The Random-access memory device of claim 1 , wherein the diode comprises an n-channel field effect transistor coupled drain-to-source between the output node of the inverter and ground, the gate of the transistor being coupled to the drain of the transistor.

11. The Random-access memory device of claim 10 , further comprising a current mirror coupled to the inverter.

12. The Random-access memory device of claim 11 , wherein the current mirror is coupled to a reference current that is not dependent on the supply voltage of the RAM cells.

13. Method for reading data from a random-access memory device having:

select lines,

bit lines,

RAM cells, each RAM cell being connected to a corresponding one of said select lines and to a corresponding one of said bit lines, and

select buffers for selecting the read-out of one out of the select lines when receiving a selection signal, whereby each or the select buffers comprises an inverter serving as driver, and a diode the method comprising the steps:

applying a selection signal to one of the select buffers,

during a first phase, providing for a current flow through the one select buffer being selected by the selection signal, the current flowing towards the select line that is controlled by the one select buffer,

during a second phase, providing for a current flow being branched so that part of current still flows towards the select line that is controlled by the one select buffer, while the remaining part of the current flows through the diode towards ground, for limiting output voltage swings at the respective select line; and

supplying a certain voltage to the select lines that is smaller than a supply voltage of the device.