Non-volatile memory test structure and method

1. A non-volatile memory test structure, comprising a plurality of memory cells arranged in rows and columns, each memory cell comprising at least a memory transistor and having a source terminal, a gate terminal and a drain terminal, wherein:

a group of said memory cells is connected in parallel,

the source terminals of the memory cells in the group are connected together and to a source line,

the drain terminals of the memory cells in the group are connected together and to a drain line,

the gate terminals of the memory cells in the group are connected together and to a gate line, and

said gate line has two connections to apply an electrical current to said gate line for using it as a heating means.

2. The non-volatile memory test structure according to claim 1 , wherein

a first number of said gaze terminals, in particular each odd numbered gate terminal, of the memory cells in the group are connected together and to a first gate line and

a second number of said gate terminals, in particular each even numbered gate terminal, of the memory cells in the group are connected together and to a second gate line.

3. The non-volatile memory test structure according to claim 1 , wherein each memory cell comprises a memory transistor and a select transistors connected in series,

said gate terminal comprises a control gaze terminal and an access gate terminal,

said control gate terminals of the memory cells in the group are connected together and to a control gate line,

said access gate terminals of the memory cells in the group are connected together and to an access gale line, and

said control gate line and/or said access gate line has two connections to apply an electrical current to said control gate line and/or said access gate line for using it as a heating means.

4. The non-volatile memory test structure according to claim 3 , wherein

a first number of said control gate terminals, in particular each odd numbered control gate terminal, of the memory cells in the group are connected together and to a first control gate line and

a second number of said control gate terminals, in particular each even numbered control gate terminal, of the memory cells in the group are connected together and to a second control gate line.

5. The non-volatile memory test structure according to claim 1 , wherein said drain line has two connections to measure an electrical voltage over said drain line for using it as temperature measuring means.

6. The non-volatile memory test structure according to claim 5 , wherein

a first number of said drain terminals, in particular each odd numbered drain terminal, of the memory cells in the group are connected together and to a first drain line and

a second number of said drain terminals, in particular each even numbered drain terminal, of the memory cells in the group are connected together and to a second drain line.

7. The non-volatile memory test structure according to claim 1 , further comprising a separate metal line having two connections to measure an electrical voltage over said metal line for using it as temperature measuring means.

8. The non-volatile memory test structure according to claim 5 , further comprising a feedback-loop from said drain line or said separate metal line, respectively, to said gate line, in particular to a power supply means for applying an electrical current to said gate line.

9. A semiconductor wafer comprising a number of non-volatile memory devices and a non-volatile memory test structure according to claim 1 .

10. A non-volatile memory test method for testing a test structure as claimed in claim 1 , said test structure comprising a plurality of memory cells arranged in rows and columns, each memory cell comprising at least a memory transistor and having a source terminal, a gate terminal and a drain terminal, said method comprising the steps of:

connecting a group of said memory cells in parallel,

connecting the source terminals of the memory cells in the group together and to a source line,

connecting the drain terminals of the memory cells in the group together and to a drain line,

connecting the gate terminals of the memory cells in the group together and to a gate line,

applying an electrical current to said gate line having two connections, using said gate line as a healing mans, and

measuring the electrical behaviour of said memory cells.

11. The method as claimed in claim 10 , wherein an endurance test, a gate stress, a drain stress and/or a continuous read stress are performed, in particular at an elevated temperature.

12. The method as claimed in claim 10 for testing a test structure as claimed in claim 2 , further comprising the steps of:

applying an electrical current to one of said numbers of gate terminals for heating the corresponding memory cells,

applying a program or erase endurance stress to the other one of said numbers of gate terminals, and

measuring the endurance stress at the memory cells associated with the gate terminals to which an endurance stress is applied before and/or after said application.

13. The method as claimed in claim 10 for testing a test structure as claimed in claim 2 , further comprising the steps of:

applying an electrical current to one of said numbers of gate terminals for heating the corresponding memory cells,

applying a negative stress to the other one of said numbers of gate terminals, and

measuring the electrical current at the drain terminals of the memory cells associated with the gate terminals to which an endurance stress is applied before and/or after said application.