IP Library Granted Patent US 7,126,364
Granted Patent B2
US 7,126,364 · App. 10/527,108 · Granted Oct 24, 2006

Interface comprising a thin PCB with protrusions for testing an integrated circuit

Assignee: Koninklijke Philips Electronics, N.V.
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Quick Facts
Patent No.
US 7,126,364
App. No.
10/527,108
Granted
Oct 24, 2006
Kind
B2
Abstract

The invention relates to a test device for testing an integrated circuit called test circuit, comprising a plurality of housings intended to be tested in a printed circuit called main circuit. The device comprises an insulating membrane of soft material having two opposite surfaces covered by two conductive layers interconnected by via holes and intended to be in contact with the test circuit and the main circuit respectively, under the influence of a pressure exerted during the test between the test circuit and the main circuit pressing the test device. Protrusions are arranged on at least one of the two layers in a predefined pattern as a function of said pins, tabs, pads etc. of the test circuit so as to ensure a contact quality between said layer and the circuit (to be tested or the main circuit) having contact with said layer under the influence of said pressing action.

Claims (26)

1. A test device for testing an integrated circuit comprising a plurality of contacts, called a test circuit, intended to be tested with the aid of a test printed circuit, called a main circuit, the test device comprising:

an insulating, non-conductive membrane of a soft material having two opposite surfaces;

two conductive layers each covering a respective one of the two opposite surfaces of said non-conductive membrane;

connection means for interconnecting said two conductive layers, said two conductive layers being adapted to come into contact with the test circuit and the main circuit respectively, under the influence of a pressing force exerted during the test between the test circuit and the main circuit deforming the test device; and

protrusions arranged on at least one off said two conductive layers according to a predefined pattern as a function of said plurality of contacts of the test circuit, so as to ensure a contact quality between said at least one layer and the test circuit or the main circuit in contact with said at least one layer, under the influence of said pressing force.

2. A test device as claimed in claim 1 , wherein said connection means are metallized holes passing through said membrane and said two layers.

3. A test device as claimed in claim 1 , wherein the test device has a thickness less than or equal to 0.4 millimeters.

4. A test device as claimed in claim 1 , wherein said non-conductive membrane has a thickness less than or equal to 0.1 millimeter.

5. A test device as claimed in claim 1 , wherein said protrusions have a height larger than or equal to 45 micrometers.

6. A test device as claimed in claim 1 , wherein said protrusions have a diameter relative to the surface of said contacts.

7. A test device as claimed in claim 1 , wherein said membrane is made of Kapton.

8. A test device as claimed in claim 1 , wherein said protrusions are arranged in pairs on each of said two layers, each element of the pair being situated on an opposite layer on either side of said connection means, so as to perform a change of the soft membrane under the influence of said pressing force.

9. A test device as claimed in claim 1 , wherein said protrusions are in the form of a truncated cone.

10. A test device as claimed in claim 1 , wherein said protrusions are engraved onto said at least one of said two conductive layers.

11. A test device as claimed in claim 1 , wherein said protrusions are arranged on both of said two conductive layers.

12. A test device as claimed in claim 11 , wherein said protrusions on one of said two conductive layers are offset from said protrusions on the other one of said two conductive layers with said connection means being arranged between said protrusions.

13. A test device as claimed in claim 1 , wherein said two conductive layers comprise two layers of conductive tracks.

14. A test device for testing an integrated circuit comprising a plurality of contacts, called a test circuit, intended to be tested w.ith the aid of a test printed circuit, called a main circuit, the test device comprising:

an insulating, non-conductive membrane of a soft material having two opposite surfaces;

two conductive layers each arranged on a respective one of the opposite surfaces of said membrane;

a connection device which interconnects said two conductive layers, said two conductive layers being adapted to contact with the test circuit and the main circuit respectively, under the influence of a pressing force exerted during the test between the test circuit and the main circuit deforming the test device, said connection device being metallized holes passing through said membrane and through said two conductive layers; and

protrusions arranged on at least one of said two conductive layers according to a predefined pattern as a function of said plurality of contacts of the test circuit, so as to ensure a contact quality between said at least one layer and the test circuit or the main circuit in contact with said at least one layer, under the influence of said pressing force.

15. A test device as claimed in claim 14 , wherein said protrusions are arranged on both of said two conductive layers.

16. A test device as claimed in claim 15 , wherein said protrusions are arranged in pairs with one of said metallized holes being situated therebetween, a first protrusion of each pair being situated on a first one of said two conductive layers on one side of a respective one of said metallized holes and a second protrusion of each pair being situated on a second one of said two conductive layers on an opposite side of said respective one of said metallized holes whereby said protrusions are thereby offset from one another.

17. A test device as claimed in claim 14 , wherein said two conductive layers comprise two layers of conductive tracks.

18. A test device as claimed in claim 14 , wherein said two conductive layers cover the respective one of the opposite surfaces of said membrane.

Assignments (4)
CHANGE OF NAME Recorded Sep 22, 2017
From: PHILIPS SEMICONDUCTORS INTERNATIONAL B.V.
To: NXP B.V.
Reel/Frame 043951/0436 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 22, 2017
From: KONINKLIJKE PHILIPS ELECTRONICS N.V.
To: PHILIPS SEMICONDUCTORS INTERNATIONAL B.V.
Reel/Frame 043955/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 15, 2006
From: KONINKLIJKE PHILIPS ELECTRONICS N.V.
To: NXP B.V.
Reel/Frame 018635/0787 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 8, 2005
From: JARDIN-LEMAGNEN, FREDERIC; SAVIN, EMMANUEL; LERUEZ, SEBASTIEN
To: KONINKLIJKE PHILIPS ELECTRONICS N.V.
Reel/Frame 016983/0481 →
Priority Claims (1)
FR 02 11243 · Sep 11, 2002 · national
Continuity (1)
Related Publication 20060033511A1 · Feb 16, 2006