IP Library Granted Patent US 7,732,272
Granted Patent B2
US 7,732,272 · App. 10/677,221 · Granted Jun 8, 2010

Method of manufacturing semiconductor element

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Quick Facts
Patent No.
US 7,732,272
App. No.
10/677,221
Granted
Jun 8, 2010
Kind
B2
Abstract

A method of manufacturing a semiconductor device includes a process of forming a gate electrode having a metallic silicide layer on a semiconductor substrate, a process of decreasing boundaries of grains on the surface of the metallic silicide layer, at least a portion of which is exposed, and a process of forming spacers comprising an oxide film on the side wall of the gate electrode; in this order. Thus, abnormal oxidation of the metallic silicide layer is avoided.

Claims (16)

1. A method of manufacturing a semiconductor element, comprising:

forming a gate electrode on a semiconductor substrate, the gate electrode having a metallic silicide layer, a metallic polysilicon layer under the metallic silicide layer, and an SiN layer on the metallic silicide layer;

after said forming of the gate electrode including the SiN layer, decreasing grain boundaries on a surface of the metallic silicide layer, at least a portion of the surface of the metallic silicide layer being exposed, said decreasing of the grain boundaries comprising performing a heat treatment on the metallic silicide layer in an atmosphere consisting of a mixture gas of chief elements of nitrogen and ammonia and an oxidizable gas of less than 100 ppm; and

forming a spacer consisting of an oxide film on a side wall of the metallic polysilicon layer and the metallic silicide layer of the gate electrode;

wherein said decreasing of the grain boundaries is performed after performing a reduced pressure process.

2. The method of claim 1 , wherein said forming of the spacer is performed after said decreasing grain boundaries on the surface of the metallic silicide layer.

3. A method of manufacturing a semiconductor element, comprising:

forming a gate electrode on a semiconductor substrate, the gate electrode having a metallic silicide layer, a metallic polysilicon layer under the metallic silicide layer, and an SiN layer on the metallic silicide layer;

after said forming of the gate electrode including the SiN layer, decreasing grain boundaries on a surface of the metallic silicide layer, at least a portion of the surface of the metallic silicide layer being exposed, said decreasing of the grain boundaries being performed after performing a reduced pressure process and comprises performing a heat treatment on the metallic silicide layer in an atmosphere including an oxidizable gas of less than 100 ppm; and

forming a spacer consisting of an oxide film on a side wall of the metallic polysilicon layer and the metallic silicide layer of the gate electrode.

4. The method of claim 3 , wherein said decreasing of the grain boundaries comprises performing a heat treatment on the metallic silicide layer in an atmosphere consisting of a chief element of nitrogen gas.

5. The method of claim 3 , wherein said decreasing of the grain boundaries comprises performing a heat treatment on the metallic silicide layer in an atmosphere consisting of a chief element of argon gas.

6. The method of claim 3 , wherein the metallic silicide layer comprises a tungsten silicide layer, and said decreasing of the grain boundaries comprises performing a heat treatment on the metallic silicide layer at temperature in a range of 700° C. to 800° C. for a time period in a range of 30 seconds to 40 seconds.

7. The method of claim 3 , wherein said decreasing of the grain boundaries comprises performing a heat treatment on the metallic silicide layer in an atmosphere including an oxidizable gas, and said reduced pressure process comprises reducing the oxidizable gas level to less than 100 ppm.

8. The method of claim 3 , wherein the metallic silicide layer comprises a tungsten silicide layer, and said decreasing of the grain boundaries comprises performing a heat treatment on the metallic silicide layer at a temperature in a range of 700° C. to 800° C. and after said performing of the reduced pressure process at a pressure of 13 Pa to 65 Pa.

9. The method of claim 3 , wherein said forming of the spacer is performed after said decreasing grain boundaries on the surface of the metallic silicide layer.

Assignments (3)
CHANGE OF NAME Recorded Mar 21, 2014
From: OKI SEMICONDUCTOR CO., LTD
To: LAPIS SEMICONDUCTOR CO., LTD.
Reel/Frame 032495/0483 →
CHANGE OF NAME Recorded Dec 18, 2008
From: OKI ELECTRIC INDUSTRY CO., LTD.
To: OKI SEMICONDUCTOR CO., LTD.
Reel/Frame 022038/0711 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 3, 2003
From: OHSAKO, TAKASHI; MORI, HIROTAKA; YOSHIDA, KATSUJI
To: OKI ELECTRIC INDUSTRY CO., LTD.
Reel/Frame 014586/0851 →