IP Library Granted Patent US 7,022,552
Granted Patent B2
US 7,022,552 · App. 10/748,258 · Granted Apr 4, 2006

Semiconductor device and method for fabricating semiconductor device

View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 7,022,552
App. No.
10/748,258
Granted
Apr 4, 2006
Kind
B2
Abstract

A semiconductor device includes a semiconductor chip having an electrode pad electrically connected to an integrated circuit and a conducting part electrically connected to the electrode pad; an insulating material formed on a side of the semiconductor chip; and a conductive pattern to extend from a top of a front side of the insulating material to the conducting part of the semiconductor chip.

Claims (16)

1. A method for manufacturing a semiconductor device comprising;

preparing a plurality of semiconductor chips each including an electrode pad electrically connected to an integrated circuit and a conducting part electrically connected to the electrode pad, wherein the electrode pad and the conducting part are formed on a front side of each of the semiconductor chips;

arranging the semiconductor chips so as to dispose a clearance between the plurality of the semiconductor chips at predetermined intervals;

filling an insulating material on the front side of each of the semiconductor chips and in the clearance between the semiconductor chips so as to expose a part of the conducting part;

forming a through hole in the insulating material at a position of the clearance;

forming a conductive pattern to extend from an inner wall of the through hole to the conducting part of the semiconductor chip; and

cutting the insulating material along the through hole and separating the plurality of the semiconductor chips into individual pieces.

2. The method according to claim 1 , wherein the insulating material is resin.

3. The method according to claim 1 , wherein the through hole is formed by laser irradiation.

4. The method according to claim 1 , further including forming a solder resist on the front side of each of the semiconductor chips so as to cover apart of the conductive pattern.

5. The method according to claim 1 , further including forming a solder ball on the conductive pattern of each of the semiconductor chips.

6. The method according to claim 1 , including detaching the semiconductor chips prior to the step of arranging the semiconductor chips, and wherein the step of arranging the semiconductor chips comprises disposing the plurality of the semiconductor chips to create the clearance at the predetermined intervals.

7. The method according to claim 1 , wherein the step of filling an insulating material on the front side of each of the semiconductor chips and in the clearance between the semiconductor chips so as to expose a part of the conducting part comprises a single step.

8. The method according to claim 1 , wherein the steps are performed in the sequence in which they are recited.

9. The method according to claim 1 , wherein no insulating material is filled into the through hole.

10. The method according to claim 1 , comprising utilizing the conductive pattern as a connecting terminal.

Assignments (2)
CHANGE OF NAME Recorded Dec 18, 2008
From: OKI ELECTRIC INDUSTRY CO., LTD.
To: OKI SEMICONDUCTOR CO., LTD.
Reel/Frame 022038/0711 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 31, 2003
From: YAMAGUCHI, TADASHI
To: OKI ELECTRIC INDUSTRY CO., LTD.
Reel/Frame 014860/0725 →