IP Library › Granted Patent US 6,946,892
Granted Patent B2
US 6,946,892 · App. 10/749,586 · Granted Sep 20, 2005

Level transforming circuit

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Quick Facts
Patent No.
US 6,946,892
App. No.
10/749,586
Granted
Sep 20, 2005
Kind
B2
Abstract

A level trasnforming circuit includes a first CMOS circuit, a first intermediate circuit, a second intermediate circuit, a second CMOS circuit, a seventh p-channel type MOS transistor, and an eighth p-channel type MOS transistor; wherein the first intermediate circuit and the second intermediate circuit form a latch circuit. To this latch circuit, writing of data is performed by way of the seventh p-channel type MOS transistor and the eighth p-channel type MOS transistor. Thus, the latch circuit is made up of a CMOS inverter. Therefore, fast operation can be obtained and drop of drivability can be restrained.

Claims (63)

1. A level transforming circuit comprising:

a first CMOS circuit which has first and second p-channel type MOS transistors connected in series between a high voltage electricity source and a first output node, and first and second n-channel type MOS transistors connected in series between said first output node and ground, wherein a gate of said first p-channel type MOS transistor which functions as a pull up switch is impressed with a first signal, wherein a gate of second n-channel type MOS transistor which functions as a pull down switch is impressed with an input signal having an amplitude between a low voltage electricity source and the ground, and wherein gates of said second p-channel type MOS transistor and said first n-channel type MOS transistor are impressed with the low voltage electricity source;

a first intermediate circuit which has a third p-channel type MOS transistor connected between the high voltage electricity source and a second output node, wherein a gate of said third p-channel type MOS transistor is impressed with said first signal, and which has a third n-channel type MOS transistor connected between said second output node and the low voltage electricity source, wherein a gate of said third n-channel type MOS transistor is impressed with said first signal;

a second intermediate circuit which has a fourth p-channel type MOS transistor connected between the high voltage electricity source and a third output node, wherein a gate of said fourth p-channel type MOS transistor is impressed with electric potential of said second output node, and which has a fourth n-channel type MOS transistor connected between the third output node and the low voltage electricity source, wherein a gate of said fourth n-channel type MOS transistor is impressed with the electric potential of said second output node, and which outputs said first signal from said third output node;

a second CMOS circuit which has fifth and sixth p-channel type MOS transistors connected in series between the high voltage electricity source and a fourth output node, and which has fifth and sixth n-channel type MOS transistors connected in series between said fourth output node and the ground, wherein a gate of said fifth p-channel type MOS transistor which functions as a pull up switch is impressed with the electric potential of said second output node, and wherein a gate of said sixth n-channel type MOS transistor which functions as a pull down switch is impressed with an inverse signal of the input signal, and wherein gates of said sixth p-channel type MOS transistor and fifth n-channel type MOS transistor are impressed with the low voltage electricity source and wherein a signal having amplitude of said high voltage and ground voltage is output from said fourth output node;

a seventh p-channel type MOS transistor which is connected between a common node of said first and second p-channel type MOS transistors and said second output node, wherein a gate of said seventh p-channel type MOS transistor is impressed with electric potential of said first output node of said first CMOS circuit;

an eighth p-channel type MOS transistor which is connected between a common node of said fifth and sixth p-channel type MOS transistors and said third output node, wherein a gate of said eighth p-channel type MOS transistor is impressed with electric potential of said fourth output node of said second CMOS circuit.

2. A level transforming circuit according to claim 1 , wherein:

a turn-on resistance of said first p-channel type MOS transistor in said first CMOS circuit is higher than a turn-on resistance of said second p-channel type MOS transistor, and a turn-on resistance of said second n-channel type MOS transistor is higher than a turn-on resistance of said first n-channel type MOS transistor;

a turn-on resistance of said fifth p-channel type MOS transistor in said second CMOS circuit is higher than a turn-on resistance of said sixth p-channel type MOS transistor, and a turn-on resistance of said sixth n-channel type MOS transistor is higher than a turn-on resistance of said fifth n-channel type MOS transistor;

a turn-on resistance of said third p-channel type MOS transistor in said first intermediate circuit is higher than a turn-on resistance of said seventh p-channel type MOS transistor; and

a turn-on resistance of said fourth p-channel type MOS transistor in said second intermediate circuit is higher than a turn-on resistance of said eighth p-channel type MOS transistor.

3. A level transforming circuit according to claim 1 , wherein:

a substrate of said third n-channel type MOS transistor in said first intermediate circuit is connected with a source of said third n-channel type MOS transistor, and a substrate of said fourth n-channel type MOS transistor in said second intermediate circuit is connected with a source of said fourth n-channel type MOS transistor; and

said substrate of said third n-channel type MOS transistor and said substrate of said fourth n-channel type MOS transistor are isolated from a substrate of each of said first, second, fifth and sixth n-channel type MOS transistors.

4. A level transforming circuit according to claim 1 , wherein:

a substrate of each of said seventh p-channel type MOS transistor and said eighth p-channel type MOS transistor is connected to a respective source of each of said seventh and eighth p-channel type MOS transistors; and

said substrate of said seventh p-channel type MOS transistor and said substrate of said eighth p-channel type MOS transistor are isolated from a substrate of each of said first to sixth n-channel type MOS transistors.

5. A level transforming circuit according to claim 1 , wherein:

said first to eighth p-channel type MOS transistors and said first to sixth n-channel type MOS transistors are formed on an active region isolated by insulating film.

6. A level transforming circuit according to claim 1 , wherein:

said first signal is a signal having an amplitude between the high voltage and the low voltage, and said first signal is output independently of said output signal.

7. A level transforming circuit comprising:

a first CMOS circuit which has first and second p-channel type MOS transistors connected in series between a high voltage electricity source and a first output node, and first and second n-channel type MOS transistors connected in series between said first output node and ground, wherein a gate of said first p-channel type MOS transistor which functions as a pull up switch is impressed with a first signal, wherein a gate of second n-channel type MOS transistor which functions as a pull down switch is impressed with an input signal having an amplitude between a low voltage electricity source and the ground, and wherein gates of said second p-channel type MOS transistor and said first n-channel type MOS transistor are impressed with the low voltage electricity source;

a first intermediate circuit which has a third p-channel type MOS transistor connected between the high voltage electricity source and a second output node, wherein a gate of said third p-channel type MOS transistor is impressed with said first signal, and which has a third n-channel type MOS transistor connected between said second output node and the low voltage electricity source, wherein a gate of said third n-channel type MOS transistor is impressed with said first signal;

a second intermediate circuit which has a fourth p-channel type MOS transistor connected between the high voltage electricity source and a third output node, wherein a gate of said fourth p-channel type MOS transistor is impressed with electric potential of said second output node, and which has a fourth n-channel type MOS transistor connected between the third output node and the low voltage electricity source, wherein a gate of said fourth n-channel type MOS transistor is impressed with the electric potential of said second output node, and which outputs said first signal from said third output node;

a second CMOS circuit which has fifth and sixth p-channel type MOS transistors connected in series between the high voltage electricity source and a fourth output node, and which has fifth and sixth n-channel type MOS transistors connected in series between said fourth output node and the ground, wherein a gate of said fifth p-channel type MOS transistor which functions as a pull up switch is impressed with the electric potential of said second output node, and wherein a gate of said sixth n-channel type MOS transistor which functions as a pull down switch is impressed with an inverse signal of the input signal, and wherein gates of said sixth p-channel type MOS transistor and fifth n-channel type MOS transistor are impressed with the low voltage electricity source, and wherein a signal having amplitude of said high voltage and ground voltage is output from said fourth output node;

a seventh p-channel type MOS transistor which is connected between a common node of said first and second p-channel type MOS transistors and said second output node, wherein a gate of said seventh p-channel type MOS transistor is impressed with electric potential of said low voltage;

an eighth p-channel type MOS transistor which is connected between a common node of said fifth and sixth p-channel type MOS transistors and said third output node, wherein a gate of said eighth p-channel type MOS transistor is impressed with electric potential of said low voltage.

8. A level transforming circuit according to claim 7 , wherein:

a turn-on resistance of said first p-channel type MOS transistor in said first CMOS circuit is higher than a turn-on resistance of said second p-channel type MOS transistor, and a turn-on resistance of said second n-channel type MOS transistor is higher than a turn-on resistance of said first n-channel type MOS transistor;

a turn-on resistance of said fifth p-channel type MOS transistor in said second CMOS circuit is higher than a turn-on resistance of said sixth p-channel type MOS transistor, and a turn-on resistance of said sixth n-channel type MOS transistor is higher than a turn-on resistance of said fifth n-channel type MOS transistor;

a turn-on resistance of said third p-channel type MOS transistor in said first intermediate circuit is higher than a turn-on resistance of said seventh p-channel type MOS transistor; and

a turn-on resistance of said fourth p-channel type MOS transistor in said second intermediate circuit is higher than a turn-on resistance of said eighth p-channel type MOS transistor.

9. A level transforming circuit according to claim 7 , wherein:

a substrate of said third n-channel type MOS transistor in said first intermediate circuit is connected with source of said third n-channel type MOS transistor, and a substrate of said fourth n-channel type MOS transistor in said second intermediate circuit is connected with a source of said fourth n-channel type MOS transistor; and

said substrate of said third n-channel type MOS transistor and said substrate of said fourth n-channel type MOS transistor are isolated from a substrate of each of said first, second, fifth and sixth n-channel type MOS transistors.

10. A level transforming circuit according to claim 7 , wherein:

a substrate of each of said seventh p-channel type MOS transistor and said eighth p-channel type MOS transistor is connected to a respective source of each of said seventh and eighth p-channel type MOS transistors; and

said substrate of said seventh p-channel type MOS transistor and said substrate of said eighth p-channel type MOS transistor are isolated from a substrate of each of said first to sixth n-channel type MOS transistors.

11. A level transforming circuit according to claim 7 , wherein:

said first to eighth p-channel type MOS transistors and said first to sixth n-channel type MOS transistors are formed on an active region isolated by insulating film.

12. A level transforming circuit according to claim 7 , wherein:

said first signal is a signal having an amplitude between the high voltage and the low voltage, and said first signal is output independently of said output signal.

13. A level transforming circuit comprising:

a first CMOS circuit which has first and second p-channel type MOS transistors connected in series between a high voltage electricity source and a first output node, and first and second n-channel type MOS transistors connected in series between said first output node and ground, wherein a gate of said first p-channel type MOS transistor which functions as a pull up switch is impressed with a first signal, wherein a gate of second n-channel type MOS transistor which functions as a pull down switch is impressed with an input signal having an amplitude between a low voltage electricity source and the ground, and wherein gates of said second p-channel type MOS transistor and said first n-channel type MOS transistor are impressed with the low voltage electricity source;

a first intermediate circuit which has a third p-channel type MOS transistor connected between the high voltage electricity source and second output node, wherein a gate of said third p-channel type MOS transistor is impressed with said first signal, and which has third n-channel type MOS transistor connected between said second output node and the low voltage electricity source, wherein a gate of said third n-channel type MOS transistor is impressed with said first signal;

a second intermediate circuit which has a fourth p-channel type MOS transistor connected between the high voltage electricity source and a third output node, wherein a gate of said fourth p-channel type MOS transistor is impressed with electric potential of second output node of said first intermediate circuit, and which has a fourth n-channel type MOS transistor connected between the third output node and the low voltage electricity source, wherein a gate of said fourth n-channel type MOS transistor is impressed with the electric potential of said second output node, and which outputs said first signal from said third output node;

a second CMOS circuit which has fifth and sixth p-channel type MOS transistors connected in series between the high voltage electricity source and a fourth output node, and which has fifth and sixth n-channel type MOS transistors connected in series between said fourth output node and the ground, wherein a gate of said fifth p-channel type MOS transistor which functions as a pull up switch is impressed with the electric potential of said second output node, and wherein a gate of said sixth n-channel type MOS transistor which functions as a pull down switch is impressed with an inverse signal of the input signal, and wherein gates of said sixth p-channel type MOS transistor and fifth n-channel type MOS transistor are impressed with the low voltage electricity source, and wherein a signal having amplitude of said high voltage and ground voltage is output from said fourth output node;

a seventh n-channel type MOS transistor which is connected between a common node of said first and second p-channel type MOS transistors and said second output node, wherein a gate of said seventh n-channel type MOS transistor is impressed with electric potential of said high voltage;

an eighth n-channel type MOS transistor which is connected between a common node of said fifth and sixth p-channel type MOS transistors and said third output node, wherein a gate of said eighth n-channel type MOS transistor is impressed with electric potential of said high voltage.

14. A level transforming circuit according to claim 13 , wherein:

a turn-on resistance of said first p-channel type MOS transistor in said first CMOS circuit is higher than a turn-on resistance of said second p-channel type MOS transistor, and a turn-on resistance of said second n-channel type MOS transistor is higher than a turn-on resistance of said first n-channel type MOS transistor;

a turn-on resistance of said fifth p-channel type MOS transistor in said second CMOS circuit is higher than a turn-on resistance of said sixth p-channel type MOS transistor, and a turn-on resistance of said sixth n-channel type MOS transistor is higher than a turn-on resistance of said fifth n-channel type MOS transistor;

a turn-on resistance of said third p-channel type MOS transistor in said first intermediate circuit is higher than a turn-on resistance of said seventh n-channel type MOS transistor; and

a turn-on resistance of said fourth p-channel type MOS transistor in said second intermediate circuit is higher than a turn-on resistance of said eighth n-channel type MOS transistor.

15. A level transforming circuit according to claim 13 , wherein:

a substrate of said third n-channel type MOS transistor in said first intermediate circuit is connected with a source of said third n-channel type MOS transistor, and a substrate of said fourth n-channel type MOS transistor in said second intermediate circuit is connected with a source of said fourth n-channel type MOS transistor; and

said substrate of said third n-channel type MOS transistor and said substrate of said fourth n-channel type MOS transistor are isolated from a substrate of each of said first, second, fifth and sixth n-channel type MOS transistors.

16. A level transforming circuit according to claim 13 , wherein:

said first to sixth p-channel type MOS transistors and said first to eighth n-channel type MOS transistors are formed on an active region isolated by insulating film.

17. A level transforming circuit according to claim 13 , wherein:

said first signal having an amplitude between the high voltage and the low voltage, and said first signal output independently of said output signal.

Assignments (2)
CHANGE OF NAME Recorded Dec 18, 2008
From: OKI ELECTRIC INDUSTRY CO., LTD.
To: OKI SEMICONDUCTOR CO., LTD.
Reel/Frame 022038/0711 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 2, 2004
From: MITARASHI, MUTSUMI
To: OKI ELECTRIC INDUSTRY CO., LTD.
Reel/Frame 014859/0530 →