Semiconductor integrated circuit
View Patent ↗The output of a differential amplifier circuit group (PA) that amplifies signals inputted to input PINs is connected to a final-stage differential amplifier circuit (PAn). The output of the differential amplifier circuit (PAn) is connected to a detection (DET) circuit. A detect signal sent from the DET circuit is outputted to the (−) side input of a comparator. A bias signal (BP) outputted from a bias circuit is inputted to the base of a PMOS transistor of a source follower circuit. An output signal (SFOUT) outputted from a source terminal thereof is inputted to the (+) side input of the comparator. A result of comparison between the bias signal (BP) and the output signal (SFOUT) is outputted from the comparator as an output signal (COMPOUT).
1. A semiconductor integrated circuit, comprising:
a plurality of differential amplifier circuits which amplify input signals, said differential amplifier circuits being connected in series respectively;
a detection which detects an output signal outputted from the final-stage differential amplifier circuit of the plurality of differential amplifier circuits and outputs a detect signal therefrom;
a bias circuit which generates a bias signal;
a source follower circuit which inputs the bias signal and outputs a signal for compensating for a variation in threshold value of the detection circuit; and
a comparator which compares the detect signal outputted from the detection circuit and the output signal of the source follower circuit.
2. A semiconductor integrated circuit according to claim 1 , wherein the detection circuit includes a first constant current source circuit and a first transistor both series-connected between a power supply node and a ground node via a first common connecting node,
a capacitive element is connected between the first common connecting node and the ground node,
the first common connecting node forms the output of the detection circuit and outputs the detect signal,
the output signal of the final-stage differential amplifier circuit is supplied to the first transistor,
and the source follower circuit includes a second constant current source circuit and a second transistor of the same conduction type as that of the first transistor, which are connected in series between the power supply node and the ground node via a second common connecting node, and the second common connecting node forms the output of the source follower circuit and outputs an output signal to the comparator.
3. A semiconductor integrated circuit according to claim 2 , wherein the first constant current source circuit is connected between the power supply node and the first common connecting node,
the first transistor is a P channel type MOS transistor having a first control electrode supplied with the output signal of the final-stage differential amplifier circuit, a first electrode connected to the first common connecting node, and a second electrode connected to the ground node,
the second constant current source circuit is connected between the power supply node and the second common connecting node,
and the second transistor is a P channel type MOS transistor having a second control electrode supplied with the bias signal, a third electrode connected to the second common connecting node and a fourth electrode connected to the ground node.
4. A semiconductor integrated circuit according to claim 2 , wherein the first constant current source circuit is connected between the ground node and the first common connecting node,
the first transistor is an N channel type MOS transistor having a first control electrode supplied with the output signal of the final-stage differential amplifier circuit, a first electrode connected to the first common connecting node and a second electrode connected to the power supply node,
the second constant current source circuit is connected between the ground node and the second common connecting node, and
the second transistor is an N channel type MOS transistor having a second control electrode supplied with the bias signal, a third electrode connected to the second common connecting node and a fourth electrode connected to the power supply node.