Fabrication method for stacked multi-chip package

1. A process for fabricating a chip having a collar portion, comprising the steps of:

providing a semiconductor wafer having a front surface, and having a back surface opposite the front surface;

forming a first plurality of mutually parallel recess portions in the back surface of the semiconductor wafer, each of the first recess portions having a first width;

forming a second plurality of mutually parallel recess portions in the back surface of the semiconductor wafer, the second plurality of recess portions being formed in a direction transverse to the first plurality of recess portions and each of the second recess portions having a second width; and

cutting the semiconductor substrate from the back side with a third width along respective longitudinal center lines of the first and second plurality of recess portions to form a plurality of chips each having a collar portion which includes a portion of the front surface of the semiconductor substrate,

wherein both the first and second widths are larger than the third width.

2. The process of claim 1 , wherein the first and second plurality of recess portions are formed by machining the back surface of the semiconductor wafer.

3. The process of claim 1 , wherein the first and second plurality of recess portions are formed by etching the back surface of the semiconductor wafer.

4. The process of claim 1 , wherein the first and second plurality of recess portions are each formed having parallel sidewalls.

5. The process of claim 1 , wherein the first and second plurality of recess portions are each formed having slanted sidewalls.

6. The process of claim 1 , wherein the first and second plurality of recess portions are each formed having arc-shaped sidewalls.

7. The process of claim 1 , further comprising the step of:

forming a plurality of electrode pads on the front surface of the semiconductor wafer.

8. The process of claim 7 , wherein the electrode pads include nickel and gold.

9. A method of fabricating a stacked multi-chip package, comprising the steps of:

fabricating a first chip having a collar portion according to a process which includes the steps of:

providing a semiconductor wafer having a front surface, and having a back surface opposite the front surface;

forming a plurality of first electrode pads on the front surface of the semiconductor wafer;

forming a first plurality of mutually parallel recess portions in the back surface of the semiconductor wafer, each of the first recess portions having a first width;

forming a second plurality of mutually parallel recess portions in the back surface of the semiconductor wafer, the second plurality of recess portions being formed in a direction transverse to the first plurality of recess portions and each of the second recess portions having a second width; and

cutting the semiconductor substrate from the back side with a third width along respective longitudinal center lines of the first and second plurality of-recess portions to form a plurality of first chips each having a collar portion which includes a main surface having thereon one of the plurality of first electrode pads, wherein both the first and second widths are larger than the third width;

fixing one of the plurality of first chips to an upper face of a substrate with the main surface of the collar portion facing away from the upper face of the substrate, such that a gap is provided between the upper face of the substrate and the collar portion; and

fixing a second chip to the upper face of the substrate in a region below the collar portion such that the second chip, which includes a main surface having thereon a second electrode pad, is disposed without contacting the first chip.

10. The method of claim 9 , further comprising the step of:

electrically connecting the second chip to the substrate with a metallic wire connected to the second electrode pad, wherein the gap is of a size such that the metallic wire does not make contact with the collar portion.

11. The method of claim 9 , further comprising the step of:

electrically connecting the first chip to the substrate with a metallic wire connected to the first electrode pad.

12. The method of claim 9 , further comprising the step of:

forming an insulation member on a side of the collar portion which faces the upper face of the substrate.

13. The method of claim 9 , wherein the collar portion has a thickness which is not less than half a thickness of the first chip.

14. The method of claim 9 , wherein the second chip is smaller in area than the collar portion of the first chip and disposed wholly within the gap.

15. The method of claim 9 , wherein the first chip comprises a logic device and the second chip comprises a storage device.