Semiconductor substrate and test pattern for the same
View Patent ↗A test pattern used for testing an electrical characteristic of a semiconductor substrate, includes: a first conductive pattern formed on a lower surface of the semiconductor substrate; a second conductive pattern formed on an upper surface of the semiconductor substrate; first and second electrodes formed on the second conductive pattern, the electrodes being connected to test probes; and a first test via-hole formed through the semiconductor substrate to connect the first and second conductive pattern electrically to each other.
1. A test pattern used for testing an electric characteristic of a semiconductor substrate, comprising:
comb-branched first and second lower wiring patterns, formed on a lower surface of the substrate, and arranged in opposition, and nested or interlocked but not in contact with each other;
first and second upper patterns formed on an upper surface of the substrate;
first and second electrodes respectively formed on the first and second upper patterns for connection to test probes;
a first via-hole through the substrate and having a conductor therein to electrically connect the first lower wiring pattern and the first upper pattern;
a second via-hole through the substrate and having a conductor therein to electrically connect the second lower wiring pattern and the second upper pattern.
2. A test pattern according to claim 1 , wherein
the electric characteristic is an insulation resistance of the semiconductor substrate.
3. A test pattern according to claim 1 , wherein the first and second upper patterns are comb-branched and arranged in opposition, the first and second upper patterns being nested or interlocked but not in contact with each other.
4. A test pattern according to claim 3 , in combination with the substrate.
5. A test pattern according to claim 1 , in combination with the substrate.