Multi chip package
View Patent ↗A multi chip package includes a substrate; a first semiconductor chip mounted on the substrate; a second semiconductor chip mounted above the first semiconductor chip; a first bonding wire electrically coupled to a first bonding pad on the first semiconductor chip; and a second bonding wire electrically coupled to a second bonding pad on the second semiconductor chip. At least the first bonding wire is of a coated wire, which comprises a conductive core and an outer insulation coating. At least the first bonding pad is of a multi layered pad, comprising a base pad formed on the first semiconductor chip; a first conductive layer formed on the base pad; and a second conductive layer formed on the first conductive layer.
1. A multi chip package comprising:
a substrate;
a first semiconductor chip mounted on the substrate;
a second semiconductor chip mounted above the first semiconductor chip;
a first bonding wire electrically coupled by wire bonding to a first wire bonding pad on the first semiconductor chip; and
a second bonding wire electrically coupled by wire bonding to a second wire bonding pad on the second semiconductor chip, wherein
at least the first bonding wire is a coated wire, which comprises a conductive core and an outer insulation coating,
at least the first wire bonding pad is a multi layered pad, comprising a base pad formed on the first semiconductor chip; a first conductive layer of nickel (Ni) formed on the base pad; and a second conductive layer of gold (Au) formed on the first conductive layer.
2. A multi chip package according to claim 1 , wherein the base pad is of aluminum.
3. A multi chip package according to claim 1 , wherein
at least the first bonding pad further comprises an insulation layer formed on the base pad so as to expose an area where the first conductive layer is electrically coupled.
4. A multi chip package according to claim 1 , wherein
the first bonding wire comprises a wire connecting the first bonding pad to the second bonding pad.
5. A multi chip package according to claim 4 , wherein
the base pad is of aluminum.
6. A multi chip package according to claim 4 , wherein
at least the first bonding pad further comprises an insulation layer formed on the base pad so as to expose an area where the first conductive layer is electrically coupled.
7. A multi chip package according to claim 1 , further comprising:
a spacer chip formed between the first semiconductor chip and the second semiconductor chip.
8. A multi chip package according to claim 7 , wherein
the base pad is of aluminum.
9. A multi chip package according to claim 7 , wherein
at least the first bonding pad further comprises an insulation layer formed on the base pad so as to expose an area where the first conductive layer is electrically coupled.
10. A multi chip package according to claim 1 , further comprising:
a resin frame arranged at an inner area of the first conductive pad to form a certain distance between the first semiconductor chip and the second semiconductor chip; and
a liquid state adhesive fixing the resin frame in position.
11. A multi chip package according to claim 10 , wherein the base pad is of aluminum.
12. A multi chip package according to claim 10 , wherein
at least the first bonding pad further comprises an insulation layer formed on the base pad so as to expose an area where the first conductive layer is electrically coupled.
13. A multi chip package according to claim 1 , wherein
a plurality of the first conductive pad are arranged in grid,
a plurality of the second conductive pad are arranged in grid,
each of the first and second conductive wires is of the coated wire, and
each of the first and second bonding pads is of the multi layered pad.
14. A multi chip package according to claim 13 , wherein the base pad is of aluminum.
15. A multi chip package according to claim 13 , wherein
at least the first bonding pad further comprises an insulation layer formed on the base pad so as to expose an area where the first conductive layer is electrically coupled.
16. A multi chip package according to claim 1 , further comprising:
a wiring sheet arranged between the first semiconductor chip and the second semiconductor chip, wherein
the wiring sheet comprises a base tape; a conductive pattern formed on the base tape; and conductive bumps formed on the conductive pattern so that the conductive bumps are electrically connected to the first conductive pad and to a bonding post, which is formed on the substrate.
17. A multi chip package according to claim 16 , wherein
the base pad is of aluminum.
18. A multi chip package according to claim 16 , wherein
at least the first bonding pad further comprises an insulation layer formed on the base pad so as to expose an area where the first conductive layer is electrically coupled.
19. A multi chip package, comprising:
a substrate;
a first semiconductor chip mounted on the substrate;
a second semiconductor chip mounted above the first semiconductor chip;
a first bonding wire electrically coupled to a first bonding pad on the first semiconductor chip; and
a second bonding wire electrically coupled to a second bonding pad on the second semiconductor chip, wherein
at least the first bonding wire is of a coated wire, which comprises a conductive core and an outer insulation coating,
at least the first bonding pad is of a multi layered pad, comprising a base pad formed on the first semiconductor chip; a first conductive layer formed on the base pad; and a second conductive layer formed on the first conductive layer
a wiring sheet arranged between the first semiconductor chip and the second semiconductor chip,
the wiring sheet comprises a base tape; a conductive pattern formed on the base tape; and conductive bumps formed on the conductive pattern so that the conductive bumps are electrically connected to the first conductive pad and to a bonding post, which is formed on the substrate, and
the wiring sheet is shaped to have an opening at its center, where none of the first conductive pad and second conductive pad is formed.
20. A multi chip package according to claim 19 , wherein
the base pad is of aluminum.
21. A multi chip package according to claim 19 , wherein
the first conductive layer is of nickel (Ni).
22. A multi chip package according to claim 19 , wherein
the second conductive layer is of gold (Au).
23. A multi chip package according to claim 19 , wherein
the base pad is of aluminum;
the first conductive layer is of nickel (Ni); and
the second conductive layer is of gold (Au).
24. A multi chip package according to claim 23 , wherein
the first and second conductive layers are formed by electroless deposition technique.
25. A multi chip package according to claim 23 , wherein
the first and second conductive layers are formed to have a thickness of 3to 5 μm and a thickness of 0.05 to 0.1 μm, respectively.
26. A multi chip package according to claim 19 , wherein
at least the first bonding pad further comprises an insulation layer formed on the base pad so as to expose an area where the first conductive layer is electrically coupled.