Method of forming a nanocluster charge storage device
View Patent ↗An integrated circuit and method of forming an integrated circuit having a memory portion minimizes an amount of oxidation of nanocluster storage elements in the memory portion. A first region of the integrated circuit has non-memory devices, each having a control electrode or gate formed of a single conductive layer of material. A second region of the integrated circuit has a plurality of memory cells, each having a control electrode of at least two conductive layers of material that are positioned one overlying another. The at least two conductive layers are at substantially a same electrical potential when operational and form a single gate electrode. In one form each memory cell gate has two polysilicon layers overlying a nanocluster storage layer.
1. A method for providing a memory, the method comprising:
providing a substrate having a first region having a first plurality of transistors and a second region having a second plurality of transistors;
forming each of the first plurality of transistors as memory cells and having a control electrode comprising at least two conductive layers of material that are positioned one overlying another, the at least two conductive layers being at substantially a same electrical potential when operational and forming a single control electrode;
forming a thin dielectric layer between the at least two conductive layers within the control electrode of each of the plurality of transistors of the first region; and
forming each of the second plurality of transistors as non-memory devices and having a control electrode comprising a single conductive layer of material that is positioned overlying the substrate.
2. The method of claim 1 wherein forming the thin dielectric layer comprises:
forming the thin dielectric layer of no more than substantially two nanometers between the at least two conductive layers within the control electrode of each of the plurality of transistors of the first region.
3. The method of claim 1 further comprising:
providing a tunnel dielectric layer overlying the substrate;
providing a layer of electrically isolated nanoclusters underlying the control electrode of each of the plurality of transistors of the first region; and
providing a control dielectric layer overlying the layer of electrically isolated nanoclusters and underlying the control electrode of each of the plurality of transistors of the first region.
4. The method of claim 1 wherein forming the at least two conductive layers of material of the first plurality of transistors further comprise:
forming a first conductive layer of in-situ doped polysilicon overlying the substrate;
performing intermediate processing prior to forming a second conductive layer of doped polysilicon overlying the first conductive layer.
5. The method of claim 4 wherein the intermediate processing further comprises cleaning the memory with an aqueous hydrofluoric acid solution.
6. The method of claim 4 wherein the intermediate processing further comprises a high temperature bake in a reducing ambient.
7. The method of claim 1 wherein forming the at least two conductive layers of material of the first plurality of transistors further comprise:
forming a first conductive layer of polysilicon overlying the substrate;
doping the first conductive layer of polysilicon by ion implantation; and
performing intermediate processing prior to forming a second conductive layer of doped polysilicon overlying the first conductive layer.
8. The method of claim 1 wherein forming the at least two conductive layers of material of the first plurality of transistors further comprise forming a first conductive layer having a first thickness and forming an overlying second conductive layer having a second thickness, and ratioing the second thickness to the first thickness in a range from substantially 1:1 to 4:1.
9. A method for forming an integrated circuit comprising:
providing a substrate having a first region and a second region;
forming a first dielectric layer overlying the first region and the second region of the substrate;
forming a charge storage layer overlying the first dielectric layer;
forming a second dielectric layer overlying the charge storage layer;
forming a first conductive layer overlying the second dielectric layer in the first region and second region;
forming a diffusion barrier layer overlying the first conductive layer;
etching the diffusion barrier layer, the first conductive layer, the second dielectric layer, the charge storage layer and the first dielectric layer from the second region;
forming a third dielectric layer overlying the second region;
removing the diffusion barrier layer from the first region;
forming a second conductive layer overlying the third dielectric layer and the first conductive layer;
forming a plurality of memory cell control electrodes in the first region from the first conductive layer and the second conductive layer;
forming a plurality of transistor control electrodes in the second region; and
completing formation of transistor current electrodes to create a plurality of memory cells in the first region and a plurality of transistors in the second region.
10. The method of claim 9 further comprising:
implementing the first dielectric layer as one of silicon dioxide, silicon oxynitride, zirconium oxide, hafnium silicate, aluminum oxide or hafnium oxide; and
implementing the second dielectric layer as one of silicon dioxide, silicon oxynitride, zirconium oxide, hafnium silicate, aluminum oxide or hafnium oxide.
11. The method of claim 9 further comprising:
implementing the charge storage layer as a layer of electrically isolated nanocrystals.
12. The method of claim 11 further comprising:
implementing the layer of electrically isolated nanocrystals as a layer of one of silicon nanocrystals, silicon-germanium nanocrystals, doped silicon nanocrystals or metal nanocrystals.
13. The method of claim 9 further comprising:
implementing the first conductive layer with doped polysilicon or a first metal having a predetermined work function; and
implementing the second conductive layer with one of doped polysilicon or a second metal.
14. The method of claim 13 further comprising:
implementing the first conductive layer with the first metal and the second conductive layer with the second metal; and
implementing the first metal and the second metal with a same metal.
15. The method of claim 9 further comprising:
forming the first conductive layer with a first thickness and the second conductive layer with a second thickness; and
ratioing the second thickness to the first thickness in a range from substantially 1:1 to 4:1.
16. A method for providing a memory, the method comprising:
providing a substrate having a first region having a first plurality of transistors and a second region having a second plurality of transistors;
forming each of the first plurality of transistors as memory cells and having a control electrode comprising at least two conductive layers of material that are positioned one overlying another, the at least two conductive layers being at substantially a same electrical potential when operational and forming a single control electrode;
providing a layer of nanoclusters underlying the control electrode of each of the plurality of transistors of the first region;
forming each of the second plurality of transistors as non-memory devices and having a control electrode comprising a single conductive layer of material that is positioned overlying the; and
forming a thin dielectric layer of no more than substantially two nanometers between the at least two conductive layers within the control electrode of each of the plurality of transistors of the first region.
17. The method of claim 16 wherein forming the at least two conductive layers of material of the first plurality of transistors further comprise forming a first conductive layer having a first thickness and forming an overlying second conductive layer having a second thickness, and ratioing the second thickness to the first thickness in a range from substantially 1:1 to 4:1.
18. The method of claim 16 further comprising:
providing a tunnel dielectric layer overlying the substrate; and
providing a control dielectric layer overlying the layer of nanoclusters and underlying the control electrode of each of the plurality of transistors of the first region.
19. A method for providing a memory, the method comprising:
providing a substrate having a first region having a first plurality of transistors and a second region having a second plurality of transistors;
forming each of the first plurality of transistors as memory cells and having a control electrode comprising at least two conductive layers of material that are positioned one overlying another, the at least two conductive layers being at substantially a same electrical potential when operational and forming a single control electrode:
providing a layer of nanoclusters underlying the control electrode of each of the plurality of transistors of the first region; and
forming each of the second plurality of transistors as non-memory devices and having a control electrode comprising a single conductive layer of material that is positioned overlying the substrate,
wherein forming the at least two conductive layers of material of the first plurality of transistors further comprise:
forming a first conductive layer of polysilicon overlying the substrate;
doping the first conductive layer of polysilicon by ion implantation; and
performing intermediate processing prior to forming a second conductive layer of doped polysilicon overlying the first conductive layer.
20. The method of claim 19 wherein forming the at least two conductive layers of material of the first plurality of transistors further comprise forming a first conductive layer having a first thickness and forming an overlying second conductive layer having a second thickness, and ratloing the second thickness to the first thickness in a range from substantially 1:1 to 4:1.
21. The method of claim 19 further comprising:
providing a tunnel dielectric layer overlying the substrate; and
providing a control dielectric layer overlying the layer of nanoclusters and underlying the control electrode of each of the plurality of transistors of the first region.