IP Library Granted Patent US 7,126,209
Granted Patent B2
US 7,126,209 · App. 11/018,541 · Granted Oct 24, 2006

Lead frame, resin-encapsulated semiconductor device, and method of producing the same

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Quick Facts
Patent No.
US 7,126,209
App. No.
11/018,541
Granted
Oct 24, 2006
Kind
B2
Abstract

A resin-encapsulated semiconductor device includes: a semiconductor chip on a surface of which a group of electrodes is disposed; a plurality of inner leads arranged along a periphery of the semiconductor chip; connecting members for connecting the electrodes of the semiconductor chip with the respective inner leads, an encapsulating resin for encapsulating surfaces of the semiconductor chip and the connecting members; and external electrodes exposed from the encapsulating resin. Each of the inner leads extends across the periphery of the semiconductor chip from an internal side to an external side of the periphery, and includes a protruded portion provided on a surface of the inner lead on an external side relative to the periphery of the semiconductor chip, the protruded portion being protruded in a thickness direction. Conductive bumps as the connecting members on the electrodes of the semiconductor chip are connected with internal portions of the respective inner leads, the internal portions being positioned inward relative to the protruded portions. The external electrodes are formed on surfaces of the protruded portions, and tip ends of the external electrodes are protruded relative to a back face of the semiconductor chip.

Claims (23)

1. A method for producing a resin-encapsulated semiconductor device, comprising:

using a lead frame that includes a frame and a plurality of inner leads that extend inward from the frame, each of the inner leads having a protruded portion provided on a surface of an external side portion thereof, the protruded portion being protruded in a thickness direction, together with a semiconductor chip having a size such that its periphery falls within an area inward relative to the protruded portions of the inner leads, the semiconductor chip having a group of electrodes;

forming conductive bumps on the electrodes of the semiconductor chip;

electrically connecting the electrodes of the semiconductor chip with internal portions of the respective inner leads via the conductive bumps, the internal portions being positioned inward relative to the protruded portions;

applying a molding sheet so as to be in close contact with surfaces of the protruded portions;

encapsulating a region including surfaces of the semiconductor chip and the conductive bumps with an encapsulating resin, with the frame and the protruded portions of the inner leads being exposed;

removing the frame from the encapsulated structure; and

providing external electrodes on surfaces of the protruded portions so that tip ends of the external electrodes are protruded relative to a back face of the semiconductor chip.

2. A method for producing a resin-encapsulated semiconductor device, comprising:

using a lead frame that includes a frame and a plurality of inner leads that extend inward from the frame, each of the inner leads having a protruded portion provided on a surface of an external side portion thereof, the protruded portion being protruded in a thickness direction, together with a first semiconductor chip and a second semiconductor chip, the first semiconductor chip having a first electrode group composed of electrodes arranged in its peripheral portion and a second electrode group composed of electrodes arranged inward relative to the first electrode group, the second semiconductor chip being smaller in size than the first semiconductor chip and having a group of electrodes;

forming first conductive bumps on the electrodes of the first electrode group of the first semiconductor chip, and forming second conductive bumps on the electrodes of the second semiconductor chip;

stacking the second semiconductor chip on a surface of the first semiconductor chip, and electrically connecting the electrodes of the second electrode group of the first semiconductor chip with the second conductive bumps on the second semiconductor chip;

applying a molding sheet so as to be in close contact with surfaces of the protruded portions;

electrically connecting the first conductive bumps with internal portions of the respective inner leads, the internal portions being positioned inward relative to the protruded portions;

encapsulating a region including surfaces of the first and second semiconductor chips and the first and second conductive bumps with an encapsulating resin, with the frame and the protruded portions of the inner leads being exposed;

removing the frame from the encapsulated structure; and

forming external electrodes on surfaces of the protruded portions so that tip ends of the external electrodes are protruded relative to a back face of the first semiconductor chip.

3. The method according to claim 2 , further comprising:

grinding a back face of the second semiconductor chip and back faces of the inner leads at the same time, after the encapsulation.

4. The method according to claim 1 , further comprising:

forming an insulation film on portions except for regions of electric connections with an external board on the surfaces of the protruded portions and the reverse surfaces of the protruded portions.

5. The method according to claim 2 , further comprising:

forming an insulation film on portions except for regions of electric connections with an external board on the surfaces of the protruded portions and the reverse surfaces of the protruded portions.

Assignments (5)
RELEASE OF SECURITY INTEREST Recorded Jun 11, 2020
From: ROYAL BANK OF CANADA
To: TESSERA, INC.; INVENSAS BONDING TECHNOLOGIES, INC. (F/K/A ZIPTRONIX, INC.); FOTONATION CORPORATION (F/K/A DIGITALOPTICS CORPORATION AND F/K/A DIGITALOPTICS CORPORATION MEMS); INVENSAS CORPORATION; TESSERA ADVANCED TECHNOLOGIES, INC; DTS, INC.; DTS LLC; PHORUS, INC.; IBIQUITY DIGITAL CORPORATION
Reel/Frame 052920/0001 →
SECURITY INTEREST Recorded Jun 1, 2020
From: ROVI SOLUTIONS CORPORATION; ROVI TECHNOLOGIES CORPORATION; ROVI GUIDES, INC.; TIVO SOLUTIONS INC.; VEVEO, INC.; INVENSAS CORPORATION; INVENSAS BONDING TECHNOLOGIES, INC.; TESSERA, INC.; TESSERA ADVANCED TECHNOLOGIES, INC.; DTS, INC.; PHORUS, INC.; IBIQUITY DIGITAL CORPORATION
To: BANK OF AMERICA, N.A.
Reel/Frame 053468/0001 →
SECURITY INTEREST Recorded Dec 2, 2016
From: INVENSAS CORPORATION; TESSERA, INC.; TESSERA ADVANCED TECHNOLOGIES, INC.; ZIPTRONIX, INC.; DIGITALOPTICS CORPORATION; DIGITALOPTICS CORPORATION MEMS; DTS, LLC; DTS, INC.; PHORUS, INC.; IBIQUITY DIGITAL CORPORATION
To: ROYAL BANK OF CANADA, AS COLLATERAL AGENT
Reel/Frame 040797/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 25, 2016
From: PANNOVA SEMIC, LLC
To: TESSERA ADVANCED TECHNOLOGIES, INC.
Reel/Frame 037581/0466 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 7, 2015
From: PANASONIC CORPORATION
To: PANNOVA SEMIC, LLC
Reel/Frame 036065/0273 →