Semiconductor memory device
To shorten the time of a test for detecting deteriorated capacitors, a semiconductor memory device having a 2T2C type memory cell structure is designed in such a way that a voltage VBL of a bit line pair which determines a voltage to be applied to ferroelectric memory cells and a voltage VPL of plate lines are so set as to satisfy a relationship of VBL=VPL<VDD where VDD is a supply voltage. This makes the size of the hysteresis loop of the ferroelectric capacitors smaller than that in case of VBL=VPL=VDD, a potential difference ΔV between data “0” and data “1” can be made smaller than an operational margin of a sense amplifier. This makes it possible to detect a deteriorated ferroelectric capacitor without conducting a cycling test.
1. A semiconductor memory device having a 1T1C type memory cell structure, wherein at a time a probing test of said semiconductor memory device is conducted, a polarization state of ferroelectric capacitors constituting adjoining memory cells which share plate lines is set to a polarization state corresponding to data “1”, irrespective of an initial polarization state of said ferroelectric capacitors, by controlling a potential of a bit line pair, a common plate line potential and a word line potential, then said common plate line potential is changed to a voltage lower than a supply voltage, and with said potential of said bit line pair being 0 V, said plate lines are driven for a predetermined time so that said ferroelectric capacitors finally come to a non-polarization state.
2. The semiconductor memory device according to claim 1 , wherein a value of said voltage lower than said supply voltage is a value determined beforehand by evaluation of a TEG (Test Element Group).