Semiconductor device and method of fabrication
View Patent ↗A semiconductor memory device employs a SONOS type memory architecture and includes a bit line diffusion layer in a shallow trench groove in which a conductive film is buried. This makes it possible to decrease the resistivity of the bit line diffusion layer without enlarging the area on the main surface of the semiconductor substrate, and to fabricate the semiconductor memory device having stable electric characteristics without enlarging the cell area. The bit line is formed by implanting ions into the sidewall of Si 3 N 4 .
1. A method of fabricating a semiconductor process comprising the steps of:
forming electrodes extending in a column direction on a semiconductor substrate;
forming sidewalls of silicon nitride on side walls of the electrodes;
implanting ions into the semiconductor substrate with a mask provided by the sidewalls of silicon nitride so that bit lines are self-aligned;
forming word lines extending in a row direction on the semiconductor substrate; and
removing portions of the electrodes extending in the column direction, which portions are located in a region in which the word lines are not provided, so that the electrodes are divided into parts.
2. The method as claimed in claim 1 , further comprising a laminate of oxide film-nitride film-oxide film (ONO film) on the main surface of the semiconductor substrate in advance, wherein the step of forming the electrodes comprises a step of removing at least the nitride film in the ONO film located in the region not coated with the electrodes.
3. The method as claimed in claim 2 , wherein the step of forming the sidewalls of silicon nitride comprises a step of implanting ions into regions that are close to the main surface of the semiconductor substrate and are located below lower ends of the side walls of the electrodes, so that core pockets can be defined in the semiconductor substrate.
4. The method as claimed in claim 1 , wherein the step of implanting ions implants ions in offset regions away from lower ends of the electrodes by a given distance.
5. The method as claimed in claim 1 , wherein the step of implanting ions comprises a step of siliciding at least exposed surfaces of the bit lines.