Non-volatile electronic memory device with NAND structure being monolithically integrated on semiconductor
View Patent ↗A non-volatile electronic memory device is integrated on a semiconductor and is of the Flash EEPROM type with a NAND architecture including at least one memory matrix divided into physical sectors, intended as smallest erasable units, and organized in rows or word lines and columns or bit lines of memory cells. At least one row or word line of a given physical sector is electrically connected to at least one row or word line of an adjacent physical sector to form a single logic sector being erasable, with the source terminals of the corresponding cells of the pair of connected rows referring to a same selection line of a source line.
1. A non-volatile memory comprising:
a memory organized into rows and columns of flash memory cells;
a first physical portion and a second physical portion of memory cells, said portions sharing columns, said first and second physical portions having different column capacitances and different minimum erasable sector sizes, and wherein rows of said first and second physical portions are coupled, the coupled rows are coupled together in groups of two or multiples of two; and
a decoupling switch to capacitively decouple the first and second physical portions.
2. The memory of claim 1 , wherein rows of said first and second physical portions are coupled, the coupled rows each occupy a same position in their respective physical portions.
3. The memory of claim 1 , wherein rows of said first and second physical portions are coupled, the coupled rows are opposite each other with respect to a same source selection line.
4. The memory of claim 1 , wherein rows of said first and second physical portions are coupled, including a logic sector comprising a number of independent drain selectors equal to a number of physical portions associated with the logic sector; and further comprising a dedicated selection line corresponding to each coupled row.
5. The memory of claim 1 , wherein rows of said first and second physical portions are coupled, the coupled rows comprise a plurality of memory cells biased in parallel on respective gate terminals; and further comprising at least one selector of each column of the coupled rows to bias a drain terminal of a memory cell belonging to one of the coupled rows.
6. The memory of claim 4 , wherein at least one column of the logic sector includes a number of elemental structures equal to a number of coupled rows coupled to a same source selection line, each elemental structure having a dedicated drain selection line.
7. The memory of claim 1 , wherein the rows of the first physical portion are electrically independent from one another.
8. The memory of claim 1 , further comprising modify and read structures; and wherein each of the first and second physical portions comprises reading and programming circuitry portions shared with one another respectively, the second physical portion being adjacent the modify and read structures.
9. The memory of claim 1 , wherein the first and second physical portions have a same number of elemental structures; and wherein each column of the first physical portion is a continuation of a column of the second physical portion.
10. The memory of claim 9 , wherein the elemental structures of the columns belonging respectively to the first and second physical portions have different column sizes and capacitances and include electrical decoupling switches to respectively separate the elemental structures from each other, said electrical decoupling switches comprising at least one of a transistor and a bank selector.
11. The memory of claim 1 , wherein the first and second physical portions each comprise respective memory cells having equivalent electrical characteristics, the respective memory cells of the second physical portion operating with a greater reading current than the respective memory cells of the first physical portion.
12. The memory of claim 6 , wherein the elemental structures comprise groups of four memory cells coupled in series with the respective at least one selector of each column.
13. The memory of claim 6 , further comprising tracks of a first metallization level coupling the rows, each track having a number of metallization shunts equal to a number of pairs of word lines referring to a metallization track of a second metallization level.
14. A method comprising:
coupling a first physical portion to a second physical portion, said first and second physical portions having different access column capacitances and different minimum erasable sector sizes, and wherein rows of said first and second physical portions are coupled, the coupled rows are coupled together in groups of two or multiples of two; and
capacitively decoupling the first and second physical portions using a decoupling switch.
15. The method of claim 14 , wherein the coupled rows each occupy a same position in their respective physical portions.
16. The method of claim 14 , wherein the coupled rows are opposite each other with respect to a same source selection line.