Methods for fabricating semiconductor devices and contacts to semiconductor devices
View Patent ↗Methods for fabricating contacts to semiconductor structures are provided. A method comprises forming two members extending from a semiconductor substrate and separated by a portion of the substrate. First and second semiconductor devices are formed in and on the substrate and each comprise a common impurity doped region that is disposed within the portion of the substrate. A dielectric layer is deposited overlying the members, the semiconductor devices, and the common impurity doped region to a thickness such that a depression overlying the impurity doped region is formed. A fill material is deposited to substantially fill the depression and a portion of the dielectric layer is etched. A masking layer is deposited and a portion of the masking layer is removed to expose the fill material. A via is formed by etching the fill material and dielectric layer and a conductive material is deposited therein.
1. A method for fabricating a semiconductor structure, the method comprising the steps of:
providing a semiconductor substrate;
forming two members extending from said semiconductor substrate, wherein said two members are separated by a portion of said semiconductor substrate;
forming a first semiconductor device and a second semiconductor device in and on said semiconductor substrate, wherein said first and second semiconductor devices each comprise a common impurity doped region that is disposed within said portion of said semiconductor substrate;
depositing a dielectric layer overlying said two members, said first and second semiconductor devices, and said common impurity doped region to a thickness such that a depression within said dielectric layer and overlying said common impurity doped region is formed;
depositing a fill material to at least substantially fill said depression;
etching a portion of said dielectric layer after the step of depositing said fill material such that said dielectric layer is etched at a faster rate than said fill material;
depositing a masking layer overlying said dielectric layer and said fill material;
removing a portion of said masking layer to expose said fill material and form an etch mask that is self-aligned to said fill material;
etching said fill material and said dielectric layer using said etch mask to form a via through said dielectric layer;
depositing a conductive material within said via such that said conductive material is electrically coupled to said impurity doped region.
2. The method of claim 1 , wherein the step of forming two members comprises the steps of:
depositing a silicon nitride layer overlying said silicon substrate;
etching said silicon nitride layer to form two trenches disposed therein;
depositing an insulating material within said trenches; and
removing said silicon nitride layer.
3. The method of claim 1 , wherein the step of forming a first semiconductor device and a second semiconductor device comprises the step of forming a first flash EEPROM memory device and a second flash EEPROM memory device.
4. The method of claim 1 , wherein the first semiconductor device has a first gate stack and the second semiconductor device has a second gate stack and wherein the step of forming a first semiconductor device and a second semiconductor device comprises the step of forming said first gate stack a distance from said second gate stack, wherein said depression has a first dimension that depends, at least in part, on said distance, and wherein the step of etching said fill material and said dielectric layer to form a via comprises the step of etching to form said via with a second dimension depending on said first dimension.
5. The method of claim 1 , wherein the step of forming two members comprises the step of forming said two members a distance from each other and wherein the step of etching said fill material and said dielectric layer to form a via comprises the step of etching said via with a dimension depending on said distance.
6. The method of claim 1 , wherein the step of forming two members comprises the step of forming said two members that extend a distance from said silicon substrate and wherein the step of etching said fill material and said dielectric layer to form a via comprises the step of etching said via with a dimension that depends on said distance.
7. The method of claim 1 , wherein the step of depositing a fill material comprises the step of depositing said fill material overlying a surface of said dielectric layer, and wherein the method further comprises the step of removing a portion of said fill material to expose said dielectric layer.
8. The method of claim 1 , further comprising the step of forming a spacer about a portion of said fill material after the step of etching a portion of said dielectric layer and before the step of depositing a masking layer.
9. The method of claim 1 , further comprising the step of removing a portion of said dielectric layer before the step of depositing a fill material.
10. The method of claim 1 , wherein the step of depositing a fill material comprises the step of depositing a silicon nitride or the step of depositing a TiN barrier layer followed by depositing a W core.
11. The method of claim 1 , further comprising the step of depositing an etch stop layer overlying said common impurity doped region before the step of depositing a dielectric layer.