IP Library Granted Patent US 7,462,529
Granted Patent B2
US 7,462,529 · App. 11/386,686 · Granted Dec 9, 2008

Nonvolatile memory device for storing multi-bit data

View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 7,462,529
App. No.
11/386,686
Granted
Dec 9, 2008
Kind
B2
Abstract

A semiconductor nonvolatile memory device for storing multi-bit data has a memory cell having a source region S and a drain region D formed at the surface of a semiconductor substrate, a gate insulator film and a control gate CG formed on a channel region CH between the source region S and the drain region D and a nonconductive trap gate in the gate insulator film. An indentation is provided at the surface of the semiconductor substrate covering a region from a position in the vicinity of the drain region in the channel region to the drain region. By providing the indentation on the drain region side of the channel region, the trap gate is positioned in the direction of a channel current flowing from the source region S to the drain region D. Then, a charge having run through the channel region CH is injected efficiently into the trap gate on the indentation.

Claims (55)

1. A method of manufacturing a semiconductor nonvolatile memory device for storing multi-bit data, the method comprising:

forming an indentation at a surface of a semiconductor substrate having a first conducting type;

forming a gate insulator film and a control gate on a horizontal surface of the semiconductor substrate and on the indentation, the gate insulator film comprising a first oxide film, a nitride film representing a nonconductive trap gate instead of a floating gate, and a second oxide film; and

forming a source region of a second conducting type opposite to the first conducting type at the horizontal surface of the semiconductor substrate and a drain region of the second conducting type at the bottom of the indentation using the control gate as a mask.

2. The method of manufacturing a semiconductor nonvolatile memory device according to claim 1 , wherein the indentation is formed in a region which is a part along the gate width, the method further comprising implanting a dopant of the first conducting type into the semiconductor substrate on both sides of the control gate using the control gate as a mask, wherein the forming the source region and the drain region includes forming the source region and the drain region by forming side wall layers on the side walls on both sides of the control gate, removing the side wall layer on the indentation, and implanting a dopant of the second conducting type into the semiconductor substrate using the control gate and the remaining side wall layer as a mask.

3. The method of manufacturing a semiconductor nonvolatile memory device according to claim 1 , wherein the forming the indentation comprises:

forming a silicon oxide film on the surface of the semiconductor substrate; and

forming a silicon nitride film on the silicon oxide film.

4. The method of manufacturing a semiconductor nonvolatile memory device according to claim 3 , wherein the forming the indentation further comprises:

forming a mask on the silicon nitride film to define the indentation; and

etching the silicon nitride film based on the mask.

5. The method of manufacturing a semiconductor nonvolatile memory device according to claim 4 , wherein the forming the indentation further comprises:

forming a region of the second conducting type in the semiconductor substrate by using the etched silicon nitride film as a mask;

forming a thick silicon oxide film by using the etched silicon nitride film as a mask; and

removing the silicon nitride film, the silicon oxide film, and the thick silicon oxide film to form the indentation.

6. The method of manufacturing a semiconductor nonvolatile memory device according to claim 5 , wherein the forming the region of the second conducting type comprises:

implanting dopant of the second conducting type.

7. The method of manufacturing a semiconductor nonvolatile memory device according to claim 5 , wherein the forming the thick silicon oxide film comprises:

utilizing a thermal oxidation atmosphere to form the thick silicon oxide film.

8. The method of manufacturing a semiconductor nonvolatile memory device according to claim 1 , wherein the first and second oxide films comprise silicon oxide, and wherein the nitride film comprises silicon nitride.

9. A method of manufacturing a semiconductor nonvolatile memory device for storing multi-bit data, the method comprising:

forming a first indentation of a first memory cell and a second indentation of a second memory cell at a surface of a semiconductor substrate having a first conducting type using a shared mask, wherein the first and second memory cells are adjacent to each other;

for the first and second memory cells, forming a gate insulator film and a control gate on a horizontal surface of the semiconductor substrate and on the respective indentation, the gate insulator film comprising a first oxide film, a nitride film representing a nonconductive trap gate instead of a floating gate, and a second oxide film; and

for the first and second memory cells, forming a source region of the second conducting type at the horizontal surface of the semiconductor substrate and a drain region of the second conducting type at the bottom of the respective indentation using the respective control gate as a mask.

10. The method of manufacturing a semiconductor nonvolatile memory device according to claim 9 , wherein the forming the first indentation comprises:

forming a silicon oxide film on the surface of the semiconductor substrate;

forming a silicon nitride film on the silicon oxide film;

forming the shared mask on the silicon nitride film to define the first and second indentations; and

etching the silicon nitride film based on the shared mask.

11. The method of manufacturing a semiconductor nonvolatile memory device according to claim 10 , further comprising:

for the first and second memory cells, forming a region of a second conducting type in the semiconductor substrate by using the etched silicon nitride film as a mask and forming a thick silicon oxide film by using the etched silicon nitride film as a mask and removing the silicon nitride film, the silicon oxide film, and the thick silicon oxide film to form the first and second indentations.

12. The method of manufacturing a semiconductor nonvolatile memory device according to claim 11 , wherein the forming the region of the second conducting type comprises:

implanting dopant of the second conducting type.

13. The method of manufacturing a semiconductor nonvolatile memory device according to claim 11 , wherein the forming the thick silicon oxide film comprises:

utilizing a thermal oxidation atmosphere to form the thick silicon oxide film.

14. The method of manufacturing a semiconductor nonvolatile memory device according to claim 9 , wherein the first and second oxide films comprise silicon oxide, and wherein the nitride film comprises silicon nitride.

15. A method of manufacturing a semiconductor nonvolatile memory device for storing multi-bit data, the method comprising:

forming an indentation at a surface of a semiconductor substrate having a first conducting type, wherein the indentation comprises a slope portion and a horizontal portion;

forming a region of the first conducting type in an area adjacent to the slope portion of the indentation;

forming a gate insulator film and a control gate on a horizontal surface of the semiconductor substrate and on the indentation, the gate insulator film comprising a first oxide film, a nitride film representing a nonconductive trap gate instead of a floating gate, and a second oxide film; and

forming a source region of a second conducting type opposite to the first conducting type at the horizontal surface of the semiconductor substrate and a drain region of the second conducting type at the bottom of the indentation using the control gate as a mask.

16. The method of manufacturing a semiconductor nonvolatile memory device according to claim 15 , wherein the forming the indentation comprises:

forming a silicon oxide film on the surface of the semiconductor substrate; and

forming a silicon nitride film on the silicon oxide film.

17. The method of manufacturing a semiconductor nonvolatile memory device according to claim 16 , wherein the forming the indentation further comprises:

forming a mask on the silicon nitride film to define the indentation; and

etching the silicon nitride film based on the mask.

18. The method of manufacturing a semiconductor nonvolatile memory device according to claim 17 , wherein the forming the indentation further comprises:

forming a region of the second conducting type in the semiconductor substrate by using the etched silicon nitride film as a mask;

forming a thick silicon oxide film by using the etched silicon nitride film as a mask; and

removing the silicon nitride film, the silicon oxide film, and the thick silicon oxide film to form the indentation.

19. The method of manufacturing a semiconductor nonvolatile memory device according to claim 18 , wherein the forming the region of the second conducting type comprises:

implanting dopant of the second conducting type.

20. The method of manufacturing a semiconductor nonvolatile memory device according to claim 18 , wherein the forming the thick silicon oxide film comprises:

utilizing a thermal oxidation atmosphere to form the thick silicon oxide film.

Assignments (7)
RELEASE OF SECURITY INTEREST Recorded Mar 16, 2022
From: MUFG UNION BANK, N.A.
To: CYPRESS SEMICONDUCTOR CORPORATION; SPANSION LLC
Reel/Frame 059410/0438 →
CORRECTIVE ASSIGNMENT TO CORRECT THE 8647899 PREVIOUSLY RECORDED ON REEL 035240 FRAME 0429. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY INTERST. Recorded Nov 3, 2020
From: CYPRESS SEMICONDUCTOR CORPORATION; SPANSION LLC
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 058002/0470 →
ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN INTELLECTUAL PROPERTY Recorded Oct 28, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: MUFG UNION BANK, N.A.
Reel/Frame 050896/0366 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 1, 2015
From: SPANSION, LLC
To: CYPRESS SEMICONDUCTOR CORPORATION
Reel/Frame 036044/0745 →
SECURITY INTEREST Recorded Mar 21, 2015
From: CYPRESS SEMICONDUCTOR CORPORATION; SPANSION LLC
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 035240/0429 →
RELEASE OF SECURITY INTEREST Recorded Mar 13, 2015
From: BARCLAYS BANK PLC
To: SPANSION LLC; SPANSION INC.; SPANSION TECHNOLOGY LLC
Reel/Frame 035201/0159 →
SECURITY AGREEMENT Recorded Jun 4, 2010
From: SPANSION LLC; SPANSION INC.; SPANSION TECHNOLOGY INC.; SPANSION TECHNOLOGY LLC
To: BARCLAYS BANK PLC
Reel/Frame 024522/0338 →