Data storing method for a non-volatile memory cell array having an error correction code
View Patent ↗An array of non-volatile memory cells includes a row with N cells and M cells. In a partial-storage step, a datum is stored in a first portion of the N cells of the row. A second portion of the N cells of the row are in an “erase” state. A first error correction code associated with the datum is stored in the M cells along with a first enable bit or guard-cell which is indicative of whether the first error correction code is active. The number of M cells, adjacent to the N cells of the row, is defined on the basis of the number N of cells. In the event the datum stored in the first portion of the N cells of the row is subsequently updated or manipulated, a second error correction code associated with the updated or manipulated datum is determined and stored in the second portion of the N cells of the row along with a second guard-cell which is indicative of whether the second error correction code is active. At that point, the first guard-cell is modified to indicate that the first error correction code is not active.
1. A storing method for an array of non-volatile memory cells comprising N cells and an error correction code, comprising:
storing a piece of information in a first portion of the array comprising a first group (X) of said N cells while maintaining a second portion of said array, comprising a second group (N−X) of said cells, in an “erase” state; and
providing an association to a first error correction code for said first group (X) of cells of said first portion using a first guard-cell to indicate said first error correction code is active.
2. The method according to claim 1 , wherein the indication of the association is provided on said N cells of said first portion of said array.
3. The method according to claim 1 , further comprising, during an update or bit manipulation of said datum stored in said first portion of said array:
generating a second error correction code for the datum in said first portion manipulated by said update or bit manipulation, with simultaneous invalidation of said first error correction code by disabling said first guard-cell;
storing said second error correction code and an enable bit in a second guard-cell to indicate said second error correction code is active; and
wherein generating and storing are repeatable for a number of times equal to an integer of the value (N−X)/M.
4. The method according to claim 3 , wherein said array is divided into two portions, the first portion containing N/2 of said N cells and the second portion containing the remaining N/2 of said N cells, and wherein update or bit manipulation is repeatable for a number of times equal to N/2 M.
5. The method according to claim 3 , wherein said N cells of said array contain one bit per cell and have said value M equal to M=log 2 N+1 and said guard cells constitute at least one cell of said M cells.
6. The method according to claim 3 , further including reading said data stored in said array comprising searching for an active one of the error correction codes, searching comprising providing a reading, by means of an input bit, of the content of said guard-cell stored in said M cells adjacent to said array and, if a disable indication is present, then providing a shift of said input bit of M positions in correspondence with said second portion of said array until an enabled guard-cell is identified and reading the corresponding error correction code associated with the enabled guard-cell, said shift being allowed for a number of times equal to an integer of the value (N−X)/M.
7. The method according to claim 6 wherein said N cells of said array contain two bits per cell, said error correction code providing the correction of one bit per one cell of said information in said first portion, said value M being equal to M=log 2 N+1, and said guard cells constituting at least one cell of said M cells.
8. The method according to claim 6 wherein said N cells of said array contain two bits per cell and providing an association comprises providing a correction of two bits of a same cell of said datum stored in said first portion, said value M being equal to M=log 2 N+2, and said guard cells constituting at least one cell of said M cells.
9. A non-volatile memory device of the type comprising:
a matrix of non-volatile memory cells organized in sectors comprising rows of N cells and at least one error correction code, each row comprising a first portion including a group of said N cells within which a datum is stored by means of a partial-storage step, and a second portion including a group (N−X) of said cells and being maintained in an “erase” state;
a first error correction code being associated with the first group of cells; and
a first guard-cell storing a first enable bit to indicate whether said first error correction code is active, said first error correction code and said first enable bit being stored in M cells adjacent to said row, with M being defined on the basis of the number N of said cells of said array.
10. The device according to claim 9 wherein said first portion contains N/2 of said N cells and said second portion contains the remaining N/2 of said N cells and wherein correction or update is repeatable for N/2 M times being M equal to M=log 2 N+1.
11. The device according to claim 9 further comprising an area for a second error correction code and a second guard-cell storing a second enable bit, generated by a correction or update of said datum stored in said first portion of the row, said second error correction code and said second guard cell being stored in M cells belonging to said second portion, said second error correction code and said second enable bit, as well and successive error correction codes and corresponding successive guard-cells being obtained by successive corrections or updates and being generated at the most for a number of times equal to an integer given by the ratio (N−X)/M.
12. The device according to claim 11 wherein said N cells, containing one bit per cell, have said value M equal to M=log 2 N+1 and in that said error correction codes occupy at the most (M−1) of said M cells and wherein said enable bits occupy at least one cell of said M cells.
13. The device according to claim 11 wherein said N cells of said array are multilevel, containing two bits per cell, one datum being stored in said first portion of said row, said error correction codes providing the correction of one bit per one cell of said first portion, said value M being equal to M=log.sub.2N+1, said error correction codes occupying at the most (M−1) of said M cells and said guard cells occupying at least one cell of said M cells.
14. The device according to claim 11 wherein said N cells of said array are multilevel, containing two bits per cell, one datum being stored in said first portion of said row, said error correction codes providing the correction of two bits per one cell of said first portion, said value M being equal to M=log 2 N+2, said error correction codes occupying at the most (M−1) of said M cells and said enable bit occupying at least one cell of said M cells.
15. A storing method for a row of non-volatile memory cells comprising N cells associated with M cells, wherein the N cells arc divided into a first and second group of cells, comprising:
storing data in the first group of cells of the N cells in the row;
storing in the M cells a first error correction code for the data stored in the first group of cells and an associated first enable bit indicating whether the first error correction code is active; and
storing in the second group of cells of the N cells in the row a second error correction code for a subsequent update or bit manipulation of the data stored in the second group of cells and an associated second enable bit indicating whether the second error correction code is active.
16. The method of claim 15 further comprising marking the first enable bit to indicate that the first error correction code is inactive if the second error correction code and second enable bit are stored in the second group of cells of the N cells in the row.
17. The method of claim 15 wherein the non-volatile memory cells store one bit per cell.
18. The method of claim 15 wherein the non-volatile memory cells store at least two bits per cell.
19. The method of claim 15 wherein the M and N cells of the row are contiguous.
20. A row of non-volatile memory cells comprising N cells associated with M cells, wherein the N cells are divided into a first and second group of cells, and data is stored data in the first group of cells of the N cells in the row, and a first error correction code for the data stored in the first group of cells and an associated first enable bit indicating whether the first error correction code is active is stored in the M cells, and a second error correction code for a subsequent update or bit manipulation of the data stored in the second group of cells and an associated second enable bit indicating whether the second error correction code is active is stored in the second group of cells of the N cells in the row.
21. The row of claim 20 wherein the first enable bit is marked to indicate that the first error correction code is inactive if the second error correction code and second enable bit are stored in the second group of cells of the N cells in the row.
22. The row of claim 20 wherein the non-volatile memory cells store one bit per cell.
23. The row of claim 20 wherein the non-volatile memory cells store at least two bits per cell.
24. The row of claim 20 wherein the M and N cells of the row are contiguous.
25. A storing method for a row of non-volatile memory cells comprising N cells associated with M cells, wherein the N cells are divided into a first and second group of cells, comprising:
storing data in the first group of cells of the N cells in the row;
storing in the M cells a first error correction code for the data stored in the first group of cells; and
storing in the second group of cells of the N cells in the row a second error correction code for a subsequent update or bit manipulation of the data stored in the first group of cells.
26. The method of claim 25 further comprising providing for each error correction code an enable bit indicative of whether the associated error correction code is active, the method further comprising marking the enable bit for the first error correction code as inactive if the second error correction code is stored in the second group of cells of the N cells in the row.
27. A row of non-volatile memory cells comprising N cells associated with M cells, wherein the N cells are divided into a first and second group of cells, and data is stored data in the first group of cells of the N cells in the row, and a first error correction code for the data stored in the first group of cells is stored in the M cells, and a second error correction code for a subsequent update or bit manipulation of the data stored in the first group of cells is stored in the second group of cells of the N cells in the row.
28. The row of claim 27 wherein each error correction code is provided with an enable bit indicative of whether the associated error correction code is active, and the enable bit for the first error correction code is marked to indicate that the first error correction code is inactive if the second error correction code is stored in the second group of cells of the N cells in the row.