Patent Assignment
Reel/Frame 032148/0068
ASSIGNMENT OF ASSIGNOR'S INTEREST
Recorded: 2014-01-31
Received: 2014-01-31
Pages: 9
Assignor
STMICROELECTRONICS NV
Executed: 2012-04-25
Assignee
NUMONYX BV
A-ONE BIZ CENTER, Z.A. VERS LA PIECE, RTE DE L'ETRAZ, 1180 ROLLE, CHX, SWITZERLAND
Covered Applications
(61)
METHOD AND CIRCUIT FOR PROGRAMMING A MEMORY CELL, IN PARTICULAR OF THE NOR FLASH TYPE
App. No. 12/104,118
→
AUTOMATIC REGULATION METHOD FOR THE REFERENCE SOURCES IN A NON-VOLATILE MEMORY DEVICE AND CORRESPONDING MEMORY DEVICE
App. No. 11/771,677
→
REFERENCE CELL LAYOUT WITH ENHANCED RTN IMMUNITY
App. No. 11/741,462
→
OPTIMIZED FLASH MEMORY ACCESS METHOD AND DEVICE
App. No. 11/787,101
→
METHOD FOR PROGRAMMING A MEMORY DEVICE SUITABLE TO MINIMIZE FLOATING GATE COUPLING AND MEMORY DEVICE
App. No. 11/732,486
→
NON VOLATILE MEMORY DEVICE ARCHITECTURE AND CORRESPONDING PROGRAMMING METHOD
App. No. 11/713,081
→
ELECTRONIC DEVICE COMPRISING NON VOLATILE MEMORY CELLS WITH OPTIMIZED PROGRAMMING AND CORRESPONDING PROGRAMMING METHOD
App. No. 11/713,074
→
OUTPUT BUFFER
App. No. 11/638,321
→
METHOD FOR PROGRAMMING OF MEMORY CELLS, IN PARTICULAR OF THE FLASH TYPE, AND CORRESPONDING PROGRAMMING ARCHITECTURE
App. No. 11/636,382
→
METHOD FOR ACCESSING IN READING, WRITING AND PROGRAMMING TO A NAND NON-VOLATILE MEMORY ELECTRONIC DEVICE MONOLITHICALLY INTEGRATED ON SEMICONCTOR
App. No. 11/561,799
→
MEMORY ARCHITECTURE WITH SERIAL PERIPHERAL INTERFACE
App. No. 11/530,199
→
MEMORY ARCHITECTURE
App. No. 11/469,754
→
HIGH VOLTAGE GENERATOR OF THE DAC-CONTROLLED TYPE
App. No. 11/463,260
→
SEALING METHOD FOR ELECTRONIC DEVICES FORMED ON A COMMON SEMICONDUCTOR SUBSTRATE AND CORRESPONDING CIRCUIT STRUCTURE
App. No. 11/457,966
→
ROW DECODER CIRCUIT AND RELATED SYSTEM AND METHOD
App. No. 11/434,564
→
DATA STORING METHOD FOR A NON-VOLATILE MEMORY CELL ARRAY HAVING AN ERROR CORRECTION CODE
App. No. 11/411,010
→
NON-VOLATILE ELECTRONIC MEMORY DEVICE WITH NAND STRUCTURE BEING MONOLITHICALLY INTEGRATED ON SEMICONDUCTOR
App. No. 11/279,385
→
INTEGRATED ELECTRONIC DEVICE HAVING A LOW VOLTAGE ELECTRIC SUPPLY
App. No. 11/401,523
→
ELECTRONIC NON-VOLATILE MEMORY DEVICE HAVING A CNAND STRUCTURE AND BEING MONOLITHICALLY INTEGRATED ON SEMICONDUCTOR
App. No. 11/401,521
→
INTEGRATED ELECTRONIC NON-VOLATILE MEMORY DEVICE HAVING NAND STRUCTURE
App. No. 11/279,384
→
NON-VOLATILE MEMORY ELECTRONIC DEVICE WITH NAND STRUCTURE BEING MONOLITHICALLY INTEGRATED ON SEMICONDUCTOR
App. No. 11/279,381
→
METHOD FOR PROGRAMMING A MEMORY DEVICE SUITABLE TO MINIMIZE THE LATERAL COUPLING EFFECTS BETWEEN MEMORY CELLS
App. No. 11/348,513
→
REMOVABLE DATA STORAGE DEVICE AND RELATED ASSEMBLING METHOD
App. No. 11/344,519
→
METHOD FOR MANUFACTURING NON-VOLATILE MEMORY DEVICES INTEGRATED IN A SEMICONDUCTOR SUBSTRATE
App. No. 11/319,798
→
METHOD FOR MANUFACTURING ELECTRONIC NON-VOLATILE MEMORY DEVICES INTEGRATED IN A SEMICONDUCTOR SUBSTRATE
App. No. 11/319,750
→
ELECTRONIC MEMORY DEVICE HAVING HIGH DENSITY NON-VOLATILE MEMORY CELLS AND A REDUCED CAPACITIVE INTERFERENCE CELL-TO-CELL
App. No. 11/300,053
→
ELECTRONIC MEMORY DEVICE HAVING HIGH INTEGRATION DENSITY NON-VOLATILE MEMORY CELLS AND A REDUCED CAPACITIVE COUPLING
App. No. 11/300,145
→
METHOD FOR CONFIGURING A VOLTAGE REGULATOR
App. No. 11/280,803
→
Flash memory device with a low pin count (LPC) communication interface
App. No. 11/261,131
→
PROGRAMMING METHOD OF MULTILEVEL MEMORIES AND CORRESPONDING CIRCUIT
App. No. 11/261,903
→
PROCESS FOR MANUFACTURING A BYTE SELECTION TRANSISTOR FOR A MATRIX OF NON VOLATILE MEMORY CELLS AND CORRESPONDING STRUCTURE
App. No. 11/258,675
→
METHOD FOR REDUCING NON-UNIFORMITY OR TOPOGRAPHY VARIATION BETWEEN AN ARRAY AND CIRCUITRY IN A PROCESS FOR MANUFACTURING SEMICONDUCTOR INTEGRATED NON-VOLATILE MEMORY DEVICES
App. No. 11/059,294
→
METHOD FOR REDUCING DEFECTS AFTER A METAL ETCHING IN SEMICONDUCTOR DEVICES
App. No. 11/009,687
→
SEALING METHOD FOR ELECTRONIC DEVICES FORMED ON A COMMON SEMICONDUCTOR SUBSTRATE AND CORRESPONDING CIRCUIT STRUCTURE
App. No. 10/971,774
→
METHOD FOR THE FABRICATION OF ISOLATION STRUCTURES
App. No. 10/909,749
→
METHOD FOR MANUFACTURING DIFFERENTIAL ISOLATION STRUCTURES IN A SEMICONDUCTOR ELECTRONIC DEVICE AND CORRESPONDING STRUCTURE
App. No. 10/890,529
→
INTEGRATED MEMORY SYSTEM
App. No. 10/805,182
→
METHOD FOR PERFORMING ERROR CORRECTIONS OF DIGITAL INFORMATION CODIFIED AS A SYMBOL SEQUENCE
App. No. 10/805,168
→
VOLTAGE REGULATION SYSTEM FOR A MULTIWORD PROGRAMMING OF A LOW INTEGRATION AREA NON VOLATILE MEMORY
App. No. 10/789,351
→
STABILIZATION METHOD FOR DRAIN VOLTAGE IN NON-VOLATILE MULTI-LEVEL MEMORY CELLS AND RELATED MEMORY DEVICE
App. No. 10/748,701
→
SEMICONDUCTOR MEMORY SYSTEM INCLUDING SELECTION TRANSISTORS
App. No. 10/746,555
→
NON-VOLATILE MEMORY CELL SENSING CIRCUIT, PARTICULARLY FOR LOW POWER SUPPLY VOLTAGES AND HIGH CAPACITIVE LOAD VALUES
App. No. 10/728,372
→
NON-VOLATILE MEMORY DEVICE ARCHITECTURE, FOR INSTANCE A FLASH KIND, HAVING A SERIAL COMMUNICATION INTERFACE
App. No. 10/727,341
→
METHOD FOR ERASING NON-VOLATILE MEMORY CELLS AND CORRESPONDING MEMORY DEVICE
App. No. 10/675,221
→
METHOD FOR MANUFACTURING SEMICONDUCTOR INTEGRATED CIRCUIT STRUCTURES
App. No. 10/631,463
→
TESTING METHOD AND DEVICE FOR NON-VOLATILE MEMORIES HAVING A LPC (LOW PIN COUNT) COMMUNICATION SERIAL INTERFACE
App. No. 10/447,293
→
PROGRAMMING METHOD OF THE MEMORY CELLS IN A MULTILEVEL NON-VOLATILE MEMORY DEVICE
App. No. 10/438,175
→
MANUFACTURING PROCESS OF AN INTERPOLY DIELECTRIC STRUCTURE FOR NON-VOLATILE SEMICONDUCTOR INTEGRATED MEMORIES
App. No. 10/356,351
→
POWER SUPPLY CIRCUIT STRUCTURE FOR A ROW DECODER OF A MULTILEVEL NON-VOLATILE MEMORY DEVICE
App. No. 10/334,126
→
REGULATION METHOD FOR THE DRAIN, BODY AND SOURCE TERMINALS VOLTAGES IN A NON-VOLATILE MEMORY CELL DURING A PROGRAM PHASE AND CORRESPONDING PROGRAM CIRCUIT
App. No. 10/331,116
→
PROGRAMMING METHOD FOR A MULTILEVEL MEMORY CELL
App. No. 10/331,161
→
LOW POWER CHARGE PUMP CIRCUIT
App. No. 10/290,030
→
SEMICONDUCTOR MEMORY SYSTEM
App. No. 10/158,554
→
INTERNAL ADDRESSING STRUCTURE OF A SEMICONDUCTOR MEMORY
App. No. 09/974,737
→
NONVOLATILE SEMICONDUCTOR MEMORY CAPABLE OF SELECTIVELY ERASING A PLURALITY OF ELEMENTAL MEMORY UNITS
App. No. 09/919,789
→
INTEGRATED CIRCUIT STRUCTURE COMPRISING CAPACITOR ELEMENT AND CORRESPONDING MANUFACTURING PROCESS
App. No. 09/912,638
→
NON-VOLATILE MEMORY WITH A CHARGE PUMP WITH REGULATED VOLTAGE
App. No. 09/909,467
→
METHOD AND A CIRCUIT STRUCTURE FOR MODIFYING THE THRESHOLD VOLTAGES OF NON-VOLATILE MEMORY CELLS
App. No. 09/908,986
→
CIRCUITAL STRUCTURE FOR PROGRAMMING DATA IN A NON-VOLATILE MEMORY DEVICE
App. No. 09/871,235
→
MANUFACTURING PROCESS FOR THE INTEGRATION IN A SEMICONDUCTOR CHIP OF AN INTEGRATED CIRCUIT INCLUDING A HIGH-DENSITY INTEGRATED CIRCUIT COMPONENTS PORTION AND A HIGH-PERFORMANCE LOGIC INTEGRATED CIRCUIT COMPONENTS PORTION
App. No. 09/858,335
→
METHOD OF FORMING LOW-RESISTIVITY CONNECTIONS IN NON-VOLATILE MEMORIES
App. No. 09/798,778
→