Electronic memory device having high density non-volatile memory cells and a reduced capacitive interference cell-to-cell
View Patent ↗An electronic memory device with a high density of non-volatile memory cells has a reduced capacitance cell-to-cell interference. The memory cells are integrated on a semiconductor substrate and are organized in a matrix of cells with word lines and bit lines connected to the cells. Each memory cell includes at least one floating gate transistor having a floating gate region projecting from the substrate, and a control gate region capacitively coupled to the floating gate region. Between the cells of opposite word lines, a lateral coating is provided that includes at least one conductive layer floating along the direction of the bit lines.
1. An electronic memory device comprising:
a semiconductor substrate;
a plurality of non-volatile memory cells integrated on said semiconductor substrate and organized in a matrix of rows and columns, each memory cell comprising at least one floating gate transistor comprising a floating gate and a control gate capacitively coupled to said floating gate; and
a plurality of word lines connected to the rows of the matrix;
a plurality of bit lines connected to the columns of the matrix; and
a coating comprising at least one floating conductive layer between memory cells of opposite word lines.
2. An electronic memory device according to claim 1 , wherein said coating laterally extends on said memory cells along a direction of the plurality of bit lines.
3. An electronic memory device according to claim 1 , wherein said coating extends on the opposite word lines along a direction of the plurality of bit lines.
4. An electronic memory device according claim 1 , wherein said coating further comprises at least one insulating layer interposed between said floating gates and said at least one floating conductive layer.
5. An electronic memory device according to claim 1 , further comprising a silicide layer above said control gates and forming with said underlying floating gates a plurality of structures having lateral spacers in a direction of said plurality of bit lines; and wherein said coating covers at least one of said plurality of structures and the lateral spacers.
6. An electronic memory device according to claim 1 , further comprising a silicide layer above said control gates and forming with said floating gates a plurality of structures; and wherein said coating covers at least laterally said plurality of structures and comprises at least one insulating layer interposed between said floating gates and said at least one floating conductive layer, said at least one insulating layer laterally extending to said plurality of underlying structures in a direction of said plurality of bit lines, and a spacer layer above said coating completely covering said semiconductor substrate.
7. An electronic memory device according to claim 1 , further comprising at least one select transistor connected to a respective bit line; and wherein said coating partially covers said at least one select transistor.
8. An electronic memory device according to claim 1 , wherein said at least one floating conductive layer comprises polysilicon.
9. An electronic memory device according to claim 1 , wherein said at least one floating conductive layer comprises a refractory metal.
10. An electronic memory device according to claim 1 , wherein said at least one floating conductive layer comprises a titanium layer.
11. An electronic memory device according to claim 4 , wherein said at least one insulating layer comprises silicon nitride.
12. An electronic memory device according to claim 4 , wherein said at least one insulating layer comprises silicon oxide.
13. An electronic memory device comprising:
a semiconductor substrate;
a plurality of non-volatile memory cells integrated on said semiconductor substrate and organized in a matrix of rows and columns, each memory cell comprising at least one floating gate transistor comprising a floating gate and a control gate capacitively coupled to said floating gate; and
a plurality of word lines connected to the rows of the matrix;
a plurality of bit lines connected to the columns of the matrix; and
a coating comprising
at least one floating conductive layer between memory cells of opposite word lines, and comprising polysilicon and a refractory metal, and
at least one insulating layer interposed between said floating gates and said at least one floating conductive layer.
14. An electronic memory device according to claim 13 , wherein said coating laterally extends on said memory cells along a direction of the plurality of bit lines.
15. An electronic memory device according to claim 13 , wherein said coating extends on the opposite word lines along a direction of the plurality of bit lines.
16. An electronic memory device according to claim 13 , further comprising a silicide layer above said control gates and forming with said underlying floating gates a plurality of structures having lateral spacers in a direction of said plurality of bit lines; and wherein said coating covers at least one of said plurality of structures and the lateral spacers.
17. An electronic memory device according to claim 13 , further comprising a silicide layer above said control gates and forming with said floating gates a plurality of structures; and wherein said coating covers at least laterally said plurality of structures and comprises at least one insulating layer interposed between said floating gates and said at least one floating conductive layer, said at least one insulating layer laterally extending to said plurality of underlying structures in a direction of said plurality of bit lines, and a spacer layer above said coating completely covering said semiconductor substrate.
18. An electronic memory device according to claim 13 , further comprising at least one select transistor connected to a respective bit line; and wherein said coating partially covers said at least one select transistor.
19. An electronic memory device according to claim 13 , wherein said at least one insulating layer comprises silicon nitride.
20. An electronic memory device according to claim 13 , wherein said at least one insulating layer comprises silicon oxide.
21. A method for making an electronic memory device comprising:
forming a plurality of non-volatile memory cells on a semiconductor substrate, the memory cells being formed in a matrix of rows and columns, each memory cell being formed comprising at least one floating gate transistor comprising a floating gate and a control gate capacitively coupled to the floating gate;
connecting a plurality of word lines to the rows of the matrix;
connecting a plurality of bit lines to the columns of the matrix; and
forming a coating comprising at least one floating conductive layer between memory cells of opposite word lines.
22. A method according to claim 21 , wherein the coating laterally extends on the memory cells along a direction of the plurality of bit lines.
23. A method according to claim 21 , wherein the coating extends on the opposite word lines along a direction of the plurality of bit lines.
24. A method according claim 21 , wherein the coating further comprises at least one insulating layer interposed between the floating gates and the at least one floating conductive layer.
25. A method according to claim 21 , further comprising forming a silicide layer above the control gates and forming with the underlying floating gates a plurality of structures having lateral spacers in a direction of the plurality of bit lines; and wherein the coating covers at least one of the plurality of structures and the lateral spacers.
26. A method according to claim 21 , further comprising forming a silicide layer above the control gates and forming with the floating gates a plurality of structures; and wherein the coating covers at least laterally the plurality of structures and comprises at least one insulating layer interposed between the floating gates and the at least one floating conductive layer, the at least one insulating layer laterally extending to the plurality of underlying structures in a direction of the plurality of bit lines, and forming a spacer layer above the coating for completely covering the semiconductor substrate.
27. A method according to claim 21 , further comprising forming at least one select transistor connected to a respective bit line; and wherein the coating partially covers the at least one select transistor.
28. A method according to claim 21 , wherein the at least one floating conductive layer comprises at least one of polysilicon, a refractory metal, and titanium.
29. A method according to claim 24 , wherein said at least one insulating layer comprises at least one of a silicon nitride and a silicon oxide.
30. A method according to claim 24 , wherein a deposition process forms the at least one insulating layer.
31. A method according to claim 24 , wherein a growing process formed the at least one insulating layer.