Method for configuring a voltage regulator
View Patent ↗A voltage regulator connected to a memory cell is configured by identifying at least a first and a second operation regions of the cell and associating the first and second operation regions with respective first and second operation conditions of the memory cell. An operative condition of the memory cell involved in a programming operation is detected, and at least a configuration signal of the regulator according to said detected operative condition is generated, this configuration signal taking a first and a second value associated with the first and second operation conditions.
1. A method for configuring a voltage regulator, the method comprising:
identifying at least a first and a second operation region of a memory cell;
associating said first and second operation regions with respective first multi-level programming and second non-multi level programming operation conditions of said memory cell;
detecting the programming operation condition of said memory cell;
generating a configuration signal applied to said voltage regulator according to said detected programming operation condition, this configuration signal taking a first and a second value associated with said first multi-level programming and second non-multi level programming operation conditions, respectively.
2. The configuration method according to claim 1 , further comprising generating at least one regulation signal by said regulator, the regulation signal being applied to a regulation element connected to said memory cell.
3. The configuration method according to claim 1 further comprising a step of generating a plurality of configuration signals of said regulator according to any number of individuated operative conditions.
4. A method, for configuring a voltage regulator, the method comprising:
identifying at least a first and a second operation region of a memory cell;
associating said first and second operation regions with respective first and second operation conditions of said memory cell;
detecting an operative condition of said memory cell involved in a programming operation;
generating a configuration signal applied to said voltage regulator according to said detected operative condition, this configuration signal taking a first and a second value associated with said first and second operation conditions, respectively;
wherein generating a configuration signal of said regulator is managed by a programming algorithm of said memory cell.
5. The configuration method according to claim 4 , wherein said programming algorithm comprises generating an enable signal and switching said enable signal into said configuration signal.
6. A method for configuring a voltage regulator, the method comprising:
identifying at least a first and a second operation region of a memory cell;
associating said first and second operation regions with respective first and second operation conditions of said memory cell;
detecting an operative condition of said memory cell involved in a programming operation;
generating a configuration signal applied to said voltage regulator according to said detected operative condition, this configuration signal taking a first and a second value associated with said first and second operation conditions, respectively;
wherein said first and second operation conditions of said memory cell are characterized by different values of the current absorbed by said memory cell.
7. The configuration method according to claim 6 , wherein said first and second operation conditions of said memory cell are respectively a multilevel programming operation characterized by a slow programming ramp and by a low value of current absorption by said memory cell and a single level programming operation characterized by a fast programming ramp and by a high value of current absorption by said cell.
8. The configuration method according to claim 7 , wherein said configuration signal configures said regulator so as to ensure a constant voltage value applied to a terminal of said memory cell, varied according to said different values of current absorbed by said memory cell.
9. A method for configuring a voltage regulator in a memory device, comprising:
determining whether a memory cell of the memory device is to be operated with a multilevel programming operation or is to be operated with a non-multi level programming operation;
generating a voltage regulator configuration signal having a first state if the memory cell is to be operated with the multilevel programming operation; and
generating the voltage regulator configuration signal having a second state if the memory cell is to be operated with the non-multi level programming operation.
10. The method of claim 9 further comprising:
generating by the voltage regulator of a first gate drive voltage if the received voltage regulator configuration signal is in the first state; and
generating by the voltage regulator of a second gate drive voltage if the received voltage regulator configuration signal is in the second state.
11. The method of claim 9 wherein said multilevel and non-multi level programming operations of said memory cell are characterized by different values of the current absorbed by said memory cell.
12. The method of claim 9 wherein generating the voltage regulator configuration signal in either of the first and second states is managed by a programming algorithm of said memory cell.
13. A method for configuring a voltage regulator in a memory device including a memory cell comprising a transistor having a drain terminal, comprising:
determining whether the memory cell is to be programmed in accordance with a first programming operation requiring a low current value at the drain terminal or in accordance with a second programming operation requiring a high current value at the drain terminal;
applying a first configuration signal to the voltage regulator in response to a first programming operation determination;
applying a second configuration signal to the voltage regulator in response to a second programming operation determination; and
generating by the voltage regulator of a control voltage whose level depends upon the applied first and second configuration signals.
14. The method of claim 13 further comprising applying the control voltage from the voltage regulator to stabilize a voltage at the drain terminal of the memory cell at substantially a same level for each of the first and second programming operations.
15. The method of claim 14 wherein applying the control voltage comprises applying the control voltage as a gate control voltage of a transistor source/drain connected in series with a column decoder circuit which is connected to the drain terminal of the memory cell.
16. The method of claim 13 wherein applying the first and second configuration signals is managed by a programming algorithm of said memory cell.