Sealing method for electronic devices formed on a common semiconductor substrate and corresponding circuit structure
View Patent ↗A method for sealing electronic devices formed on a semiconductor substrate includes forming at least one first conductive layer on a first portion of the semiconductor substrate for defining electronic devices, and forming a second conductive layer on a second portion of semiconductor substrate for also defining electronic devices. First regions are formed in the at least one first conductive layer for defining electronic devices, and a first sealing layer is formed on the whole semiconductor substrate to seal the first regions. Second regions are formed in the second conductive layer for defining electronic devices, and a second sealing layer is formed on the whole semiconductor substrate to seal the second regions.
1. A method for sealing electronic devices formed on a semiconductor substrate comprising:
forming at least one first conductive layer on a first portion of the semiconductor substrate;
forming a second conductive layer on a second portion of the semiconductor substrate;
forming a first plurality of regions in the at least one first conductive layer for defining first electronic devices on the first portion of the semiconductor substrate;
forming a first sealing layer on the first plurality of regions for sealing the first electronic devices, and on the second conductive layer;
forming a second plurality of regions in the second conductive layer for defining second electronic devices on the second portion of the semiconductor substrate and so that the second electronic devices have at least portions of the first sealing layer thereon; and
forming a second sealing layer on the second plurality of regions for sealing the second electronic devices having at least portions of the first sealing layer thereon, and on the first sealing layer sealing the first electronic devices.
2. A method according to claim 1 , wherein the first sealing layer has a first thickness, and the second sealing layer has a second thickness less than the first thickness.
3. A method according to claim 2 , wherein the second thickness is within a range of about 1 to 3 nm, and the first thickness is within a range of about 3 to 7 nm.
4. A method according to claim 1 , further comprising removing portions of the first sealing layer on the second conductive layer before forming the second plurality of regions.
5. A method according to claim 1 , wherein forming the first plurality of regions comprises:
forming a photoresist layer on the first and second conductive layers;
etching the photoresist layer on the first conductive layer for forming the first plurality of regions; and
removing the photoresist layer.
6. A method according to claim 1 , wherein forming the second plurality of regions comprises;
forming a photoresist layer on the first sealing layer on the first plurality of regions, and on the second conductive layer;
etching the photoresist layer on the second conductive layer for forming the second plurality of regions; and
removing the photoresist layer.
7. A method according to claim 1 , wherein forming the at least one first conductive layer comprises forming a lower conductive layer, a dielectric layer on the lower conductive layer, and an upper conductive layer on the dielectric layer.
8. A method according to claim 7 , wherein the upper conductive layer is formed when the second conductive layer is formed.
9. A method for making an integrated circuit comprising:
forming at least one first conductive layer on a first portion of the semiconductor substrate;
forming a second conductive layer on a second portion of the semiconductor substrate;
forming a plurality of memory cells in the at least one first conductive layer and the first portion of the semiconductor substrate;
forming a first sealing layer on the plurality of memory cells, and on the second conductive layer;
forming a plurality of transistors in the second conductive layer on the second portion of the semiconductor substrate and so that the plurality of transistors have at least portions of the first sealing layer thereon; and
forming a second sealing layer on the plurality of transistors having at least portions of the first sealing layer thereon, and on the first sealing layer sealing the plurality of memory cells, the second sealing layer having a thickness less than a thickness of the first sealing layer.
10. A method according to claim 9 , wherein the second sealing layer has a thickness within a range of about 1 to 3 nm, and the first sealing layer has a thickness within a range of about 3 to 7 nm.
11. A method according to claim 9 , wherein forming the plurality of memory cells comprises:
forming a photoresist layer on the first and second conductive layers;
etching the photoresist layer on the first conductive layer for forming the plurality of memory cells; and
removing the photoresist layer.
12. A method according to claim 9 , wherein forming the plurality of transistors comprise:
forming a photoresist layer on the first sealing layer on the plurality of memory cells, and on the second conductive layer;
etching the photoresist layer on the second conductive layer for forming the plurality of transistors; and
removing the photoresist layer.