Method for manufacturing semiconductor integrated circuit structures
View Patent ↗A method for manufacturing circuit structures integrated in a semiconductor substrate that includes regions, in particular isolation regions, includes the steps of:—depositing a conductive layer to be patterned onto the semiconductor substrate;—forming a first mask of a first material on the conductive layer;—forming a second mask made of a second material that is different from the first and provided with first openings of a first size having spacers formed on their sidewalls to uncover portions of the first mask having a second width which is smaller than the first;—partly etching away the conductive layer through the first and second masks such to leave grooves of the second width;—removing the second mask and the spacers; and—etching the grooves through the first mask to uncover the regions provided in the substrate and form conductive lines.
1. A method for manufacturing circuit structures integrated in a semiconductor substrate that includes isolation regions, the method comprising the steps of:
depositing a conductive layer onto said semiconductor substrate;
forming a first mask of a first material on said conductive layer;
forming a second mask made of a second material that is different from the first material and provided with first openings of a first width having spacers formed on sidewalls of the first openings to uncover portions of said first mask having a second width which is smaller than the first width;
partly etching away said conductive layer through said first and second masks such to form grooves of said second width and leaving thin portions of said conductive layer covering said regions provided in said substrate;
removing said second mask and said spacers; and
after removing said second mask and said spacers, etching said thin portions of said conductive layer through the grooves to uncover said regions provided in said substrate and form conductive lines from the conductive layer.
2. A method for manufacturing circuit structures according to claim 1 , wherein said spacers are obtained by polymerizing plasma etching through said second mask.
3. A method for manufacturing circuit structures according to claim 1 , wherein said first and second masks respectively are made of first and second protective layers.
4. A method for manufacturing circuit structures according to claim 3 , wherein said first and second protective layers are made out of materials that are highly selectively etchable with respect to said conductive layer.
5. A method for manufacturing circuit structures according to claim 3 , wherein said first and second protective layers are selectively etchable materials to each other.
6. A method for manufacturing circuit structures according to claim 3 , wherein said first and second protective layers are dielectric layers.
7. A method for manufacturing circuit structures according to claim 6 , wherein said first protective layer is a layer of silicon nitride.
8. A method for manufacturing circuit structures according to claim 6 , wherein said second protective layer is a layer of silicon oxide.
9. A method for manufacturing circuit structures according to claim 3 , wherein said spacers are formed by the following steps:
depositing a third protective layer onto said second mask after said openings are formed; and
removing portions of said third protective layer to uncover portions of said first mask having a second width smaller than the first.
10. A method for manufacturing conductive lines, the method comprising:
forming a conductive layer;
forming a first protective layer of a first material on the conductive layer;
forming a second protective layer on the first protective layer, the second protective layer being of a second material that is different from the first material;
forming first openings of a first width in the second protective layer;
forming spacers on sidewalls of the first openings to reduce the first openings to a second width that is smaller than the first width;
etching, after forming the spacers, the first protective layer through the first openings in the second protective layer to produce second openings of the second width in the first protective layer without exposing a region underlying the conductive layer;
removing the spacers; and
after removing the spacers, etching the conductive layer through the second openings in the first protective layer to produce third openings of the second width in the conductive layer and thereby form the conductive lines from the conductive layer.
11. The method of claim 10 wherein the first and second protective layers are made out of materials that are highly selectively etchable with respect to the conductive layer.
12. The method of claim 10 wherein the first and second protective layers are selectively etchable materials with respect to each other.
13. The method of claim 10 wherein the first and second protective layers are dielectric layers.
14. The method of claim 10 wherein the spacers are formed by the following steps:
depositing a third protective layer onto the second protective layer and into the first openings; and
removing portions of the third protective layer outside of the first openings and portions of the third protective layer in central portions of the first openings while leaving portions of the third protective layer along the sidewalls of the first openings as the spacers.
15. The method of claim 10 wherein the spacers are obtained by polymerizing plasma etching of the second protective layer to produce the first openings.
16. The method of claim 10 wherein the first protective layer is a layer of silicon nitride.
17. The method of claim 16 wherein the second protective layer is a layer of silicon oxide.
18. A method, comprising:
forming a first layer;
forming a first protective layer of a first material on the first layer;
forming a second protective layer on the first protective layer, the second protective layer being of a second material that is different from the first material;
forming a first opening of a first width in the second protective layer;
forming spacers on sidewalls of the first opening to reduce the first opening to a second width that is smaller than the first width, wherein the forming spacers step uncovers a portion of the first protective layer having the second width, and wherein the spacers are obtained by polymerizing plasma etching of the second protective layer to produce the first opening;
etching the first protective layer through the first opening in the second protective layer to produce a second opening of the second width in the first protective layer; and
etching the first layer through the second opening in the first protective layer to produce a third opening in the first layer.
19. The method of claim 18 wherein the first and second protective layers are made out of materials that are highly selectively etchable with respect to the first layer.
20. The method of claim 18 wherein the first and second protective layers are selectively etchable materials with respect to each other.
21. The method of claim 18 wherein the spacers are formed by the following steps:
depositing a third protective layer onto the second protective layer and into the first opening; and
removing portions of the third protective layer outside of the first opening and a portion of the third protective layer in a central portion of the first opening while leaving portions of the third protective layer along the sidewalls of the first opening as the spacers.
22. A method for manufacturing conductive lines, the method comprising:
forming a conductive layer;
forming a first protective layer of a first material on the conductive layer;
forming a second protective layer on the first protective layer, the second protective layer being of a second material that is different from the first material, wherein the second protective layer is a layer of silicon oxide;
forming first openings of a first width in the second protective layer;
forming spacers on sidewalls of the first openings to reduce the first openings to a second width that is smaller than the first width;
etching the first protective layer through the first openings in the second protective layer to produce second openings of the second width in the first protective layer; and
etching the conductive layer through the second openings in the first protective layer to produce third openings of the second width in the conductive layer and thereby form the conductive lines from the conductive layer.
23. The method of claim 22 wherein the first and second protective layers are made out of materials that are highly selectively etchable with respect to the conductive layer.
24. The method of claim 22 wherein the first and second protective layers are selectively etchable materials with respect to each other.
25. The method of claim 22 wherein the first and second protective layers are dielectric layers.
26. The method of claim 22 wherein the first protective layer is a layer of silicon nitride.
27. A method for manufacturing conductive lines, the method comprising:
forming a conductive layer;
forming a first protective layer of a first material on the conductive layer;
forming a second protective layer on the first protective layer, the second protective layer being of a second material that is different from the first material;
forming first openings of a first width in the second protective layer;
forming spacers on sidewalls of the first openings to reduce the first openings to a second width that is smaller than the first width, wherein the spacers are obtained by polymerizing plasma etching of the second protective layer to produce the first openings;
etching the first protective layer through the first openings in the second protective layer to produce second openings of the second width in the first protective layer; and
etching the conductive layer through the second openings in the first protective layer to produce third openings of the second width in the conductive layer and thereby form the conductive lines from the conductive layer.
28. The method of claim 27 wherein the first and second protective layers are made out of materials that are highly selectively etchable with respect to the conductive layer.
29. The method of claim 27 wherein the first and second protective layers are selectively etchable materials with respect to each other.
30. The method of claim 27 wherein the first and second protective layers are dielectric layers.
31. The method of claim 27 wherein the first protective layer is a layer of silicon nitride.
32. A method for manufacturing circuit structures integrated in a semiconductor substrate that includes isolation regions, the method comprising the steps of:
depositing a conductive layer onto said semiconductor substrate;
forming a first mask of a first material on said conductive layer;
forming a second mask made of a second material that is different from the first material and provided with first openings of a first width having spacers formed on sidewalls of the first openings to uncover portions of said first mask having a second width which is smaller than the first width, wherein said first mask and said second mask are made out of materials that are highly selectively etchable with respect to said conductive layer;
partly etching away said conductive layer through said first and second masks such to form grooves of said second width;
removing said second mask and said spacers; and
etching said grooves through said first mask to uncover said regions provided in said substrate and form conductive lines from the conductive layer.
33. The method of claim 32 wherein said first and second masks are made of first and second protective layers, respectively.
34. The method of claim 33 wherein said first and second protective layers are dielectric layers.
35. The method of claim 34 wherein said first protective layer is a layer of silicon nitride.
36. The method of claim 35 wherein said second protective layer is a layer of silicon oxide.