Voltage regulation system for a multiword programming of a low integration area non volatile memory
View Patent ↗The invention relates to a voltage regulation system for multiword programming in non volatile memories, for example of the Flash type, with low circuit area occupation, wherein memories comprise at least a memory cell matrix organized in cell rows and columns and with corresponding circuits responsible for addressing, decoding, reading, writing and erasing the memory cell content. The memory cells have drain terminals connected to matrix columns and are biased in the programming step with a predetermined voltage value by means of program load circuits associated to each matrix column. In parallel with each program load circuit, a conduction-to-ground path is enabled by a controlled active element.
1. A voltage regulation system for multiword programming in a non volatile memory, for example of the Flash type, with low circuit area occupation, wherein the memory comprises at least a memory cell matrix organized in cell rows and columns and with corresponding circuits responsible for addressing, decoding, reading, writing and erasing the memory cell content, each cell having a drain terminal connected to a matrix column and biased in the programming step with a predetermined voltage value by a program load circuit associated with each matrix column, the system further including, in parallel with each program load circuit, a current sinking conduction-to-ground path that includes an enabling controlled active element.
2. The system according to claim 1 , wherein the controlled active element is a pass transistor receiving on the control terminal thereof a first enabling signal.
3. The system according to claim 2 , wherein the first enabling signal is complementary to a second enabling signal applied to the corresponding program load circuit.
4. The system according to claim 1 , wherein the conduction-to-ground path is a redundant current path.
5. The system according to claim 1 , wherein the conduction-to-ground path is a dummy current path.
6. A non-volatile memory circuit, comprising:
a non-volatile memory cell coupled to a bit line and a word line;
a bit line biasing circuit coupled to the bit line; and
a selectively actuated current sinking conduction to ground path coupled to the bit line in parallel with the bit line biasing circuit.
7. The circuit of claim 6 wherein the non-volatile memory cell comprises a floating gate transistor having its drain terminal connected to the bit line and its gate connected to the word line.
8. The circuit of claim 6 wherein the selectively actuated conduction to ground path is coupled to the bit line through at least a column decoding circuit.
9. The circuit of claim 6 wherein the selectively actuated conduction to ground path is coupled to the bit line through at least a bit line biasing circuit.
10. A non-volatile memory comprising:
a non-volatile memory cell coupled to a bit line and a word line;
a bit line biasing circuit; and
a selectively actuated current sinking conduction to ground path coupled to the bit line through at least a bit line biasing circuit;
wherein the bit line biasing circuit and the selectively actuated conduction to ground path are oppositely activated.
11. A non-volatile memory, comprising:
a memory matrix including a plurality of memory cells arranged in columns, each associated with a bit line, and rows, each associated with a word line;
a column programming circuit coupled between a programming voltage source and each bit line and activated in response to a first control signal; and
a bypass path circuit for each bit line coupled in parallel with the column programming circuit between the programming voltage source and ground and activated in response to a second control signal.
12. The memory of claim 11 wherein each memory cell comprises a floating gate transistor having its drain terminal connected to the bit line and its gate connected to the word line.
13. The memory of claim 11 further including a column decoding circuit for each column.
14. The memory of claim 11 wherein the bypass path circuit comprises a pass transistor for each column coupled between the programming voltage source and ground.
15. A non-volatile memory, comprising:
a memory matrix including a plurality of memory cells arranged in columns, each associated with a bit line, and rows, each associated with a word line;
a column programming circuit coupled between a programming voltage source and each bit line and activated in response to a first control signal; and
a bypass path circuit for each bit line coupled between the programming voltage source and ground and activated in response to a second control signal;
wherein, for each column, the first and second control signals are complementary.
16. A voltage regulation system for a non volatile memory including a memory cell matrix organized in cell rows and columns, comprising:
a program load circuit for each matrix column that biases each memory cell in a selected matrix column with a predetermined voltage value during a programming operation; and
a current sinking conduction-to-ground path for each matrix column, each path being connected in parallel with the program load circuit and enabled when its associated matrix column is not selected during the programming operation.
17. The system of claim 16 wherein each memory cell comprises a floating gate transistor having its drain terminal connected to a bit line for a column and its gate connected to a word line for a row.
18. The system of claim 16 further including a column decoding circuit for each column.
19. The system according to claim 16 , wherein the conduction to ground path includes a controlled active element comprising a pass transistor receiving on a control terminal thereof a first enabling signal.
20. A voltage regulation system for a non volatile memory including a memory cell matrix organized in cell rows and columns, comprising:
a program load circuit for each matrix column that biases each memory cell in a selected matrix column with a predetermined voltage value during a programming operation; and
a current sinking conduction-to-ground path for each matrix column, each path being enabled when its associated matrix column is not selected during the programming operation;
wherein the conduction to ground path includes a controlled active element comprising a pass transistor receiving on a control terminal thereof a first enabling signal; and
wherein the first enabling signal is complementary to a second enabling signal applied to the corresponding program load circuit.
21. A voltage regulation system for a non volatile memory including a memory cell matrix organized in cell rows and columns, comprising:
a program load circuit for each matrix column that biases each memory cell in a selected matrix column with a predetermined voltage value during a programming operation; and
a current sinking conduction-to-ground path for each matrix column, each path being enabled when its associated matrix column is not selected during the programming operation;
wherein the conduction-to-ground path is a redundant current path for the program load circuit.
22. A voltage regulation system for a non volatile memory including a memory cell matrix organized in cell rows and columns, comprising:
a program load circuit for each matrix column that biases each memory cell in a selected matrix column with a predetermined voltage value during a programming operation; and
a current sinking conduction-to-ground path for each matrix column, each path being enabled when its associated matrix column is not selected during the programming operation;
wherein the conduction-to-ground path is a dummy current path for the program load circuit.