Non-volatile memory cell sensing circuit, particularly for low power supply voltages and high capacitive load values
View Patent ↗A sensing circuit for a memory cell includes a first bias current generator connected between a first voltage reference and a first inner circuit node, and a second reference current generator connected to the first voltage reference. A comparator having a first input terminal is connected to a comparison circuit node that is connected to the second reference current generator, a second input terminal is connected to a circuit node that is connected to the first inner circuit node, and an output terminal forms an output terminal of the sensing circuit. A cascode-configured bias circuit is connected between the inner circuit node and a matching circuit node. The cascode-configured bias circuit is also connected to a second voltage reference. A current/voltage conversion stage is connected to the matching circuit node, to the comparison circuit node, and to a third voltage reference.
1. A sensing circuit for a memory cell and comprising:
a first bias current generator connected between a first voltage reference and a first inner circuit node;
at least one second reference current generator connected to the first voltage reference;
a comparator having a first input terminal connected to a comparison circuit node that is connected to said at least one second reference current generator, a second input terminal connected to a circuit node that is connected to the first inner circuit node, and at least one output terminal forming at least one output terminal of the sensing circuit;
a cascode-configured bias circuit connected between the inner circuit node and a matching circuit node, said cascode-configured bias circuit also connected to a second voltage reference; and
a current/voltage conversion stage connected to the matching circuit node, to the comparison circuit node, and to a third voltage reference.
2. A sensing circuit according to claim 1 , wherein the first voltage reference is a supply voltage, and a third voltage reference is ground.
3. A sensing circuit according to claim 1 , wherein said cascode-configured bias circuit comprises:
a first transistor connected between the inner circuit node and the matching circuit node, said first transistor comprising a control terminal; and
an operational amplifier having an output terminal connected to the control terminal of said first transistor, a first input terminal connected to the second voltage reference and a second input terminal connected to the output terminal.
4. A sensing circuit according to claim 3 , wherein said first transistor comprises a P-channel MOS transistor.
5. A sensing circuit according to claim 1 , wherein said current/voltage conversion stage comprises:
a second transistor that is diode-configured and is connected between the matching circuit node and the third voltage reference, said second transistor comprising a control terminal; and
a third transistor connected between the comparison circuit node and the third voltage reference, said third transistor comprising a control terminal connected to the control terminal of said second transistor.
6. A sensing circuit according to claim 5 , wherein said second transistor and said third transistor comprise N-channel MOS transistors.
7. A sensing circuit according to claim 1 , wherein said at least one second reference current generator comprises a plurality of reference current generators forming a plurality of branches connected to a plurality of inputs of said comparator; and wherein said at least one output terminal of said comparator comprises a plurality of output terminals for forming a plurality of output terminals of the sensing circuit.
8. A memory comprising:
at least one memory cell; and
at least one sensing circuit connected to said at least one memory cell and comprising
a first bias current generator connected to a first voltage reference,
at least one second reference current generator connected to the first voltage reference,
a comparator having a first input terminal connected to a comparison circuit node that is connected to said at least one second reference current generator, a second input terminal connected to a circuit node that is connected to said first bias current generator, and at least one output terminal forming at least one output terminal of the sensing circuit,
a bias circuit connected to said first bias current generator, and
a current/voltage conversion stage connected to said bias circuit, to the comparison circuit node, and to a second voltage reference.
9. A memory according to claim 8 , wherein the first voltage reference is a supply voltage, and the second voltage reference is ground.
10. A memory according to claim 8 , wherein said bias circuit comprises:
a first transistor connected between said first bias current generator and said current/voltage conversion stage, said first transistor comprising a control terminal; and
an operational amplifier having an output terminal connected to the control terminal of said first transistor, a first input terminal connected to a third voltage reference and a second input terminal connected to the output terminal.
11. A memory according to claim 10 , wherein said first transistor comprises a P-channel MOS transistor.
12. A memory according to claim 8 , wherein said current/voltage conversion stage comprises:
a second transistor that is diode-configured and is connected between said bias circuit and the second voltage reference, said second transistor comprising a control terminal; and
a third transistor connected between the comparison circuit node and the second voltage reference, said third transistor comprising a control terminal connected to the control terminal of said second transistor.
13. A memory according to claim 12 , wherein said second transistor and said third transistor comprise N-channel MOS transistors.
14. A memory according to claim 8 , wherein said at least one second reference current generator comprises a plurality of reference current generators forming a plurality of branches connected to a plurality of inputs of said comparator; and wherein said at least one output terminal of said comparator comprises a plurality of output terminals for forming a plurality of output terminals of said sensing circuit.
15. A method for forming a sensing circuit for a memory cell, the method comprising:
connecting a first bias current generator between a first voltage reference and a first inner circuit node;
connecting at least one second reference current generator to the first reference voltage;
connecting a comparator having a first input terminal to a comparison circuit node that is connected to the at least one second reference current generator, a second input terminal connected to a circuit node that is connected to the first inner circuit node, and at least one output terminal forming at least one output terminal of the sensing circuit;
connecting a bias circuit between the inner circuit node and a matching circuit node, the bias circuit also being connected to a second voltage reference; and
connecting a current/voltage conversion stage to the matching circuit node, to the comparison circuit node, and to a third voltage reference.
16. A method according to claim 15 , wherein the first voltage reference is a supply voltage, and the third voltage reference is ground.
17. A method according to claim 15 , wherein the bias circuit comprises:
a first transistor connected between the inner circuit node and the matching circuit node, the first transistor comprising a control terminal; and
an operational amplifier having an output terminal connected to a control terminal of the first transistor, a first input terminal connected to the third voltage reference and a second input terminal connected to the output terminal.
18. A method according to claim 17 , wherein the first transistor comprises a P-channel MOS transistor.
19. A method according to claim 15 , wherein the current/voltage conversion stage comprises:
a second transistor that is diode-configured and is connected between the matching circuit node and the third voltage reference, the second transistor comprising a control terminal; and
a third transistor connected between the comparison circuit node and the third voltage reference, the third transistor comprising a control terminal connected to the control terminal of the second transistor.
20. A method according to claim 19 , wherein the second transistor and the third transistor comprise N-channel MOS transistors.
21. A method according to claim 15 , wherein the at least one second reference current generator comprises a plurality of reference current generators forming a plurality of branches connected to a plurality of inputs of the comparator; and wherein the at least one output terminal of the comparator comprises a plurality of output terminals for forming a plurality of output terminals of the sensing circuit.