Flash memory device with a low pin count (LPC) communication interface
The Flash memory device with a Low Pin Count (LPC) communication interface includes a memorization block or Flash core including a matrix of non volatile memory cells, with associated circuit portions for reading, modifying and erasing the data contained in the memory. An interface block associated with the LPC communication interface includes at least an address block, a data block and a state machine enabling the data flow from and towards the memorization block. Advantageously, the data block of the interface block is doubled in a portion provided to contain the read data and in a portion provided to contain write data. In the memorization block, respective address decoders are provided for the read and write steps of the memory matrix. The device includes an architecture of the multibank type and the logic necessary for the execution of a “Dual Operations” mode. In this way it is possible to simultaneously perform a modify operation in a memory bank and a read operation in another bank.
1. A memory device with a Low Pin Count (LPC) communication interface, comprising:
a memory block, including:
a write address decoder;
a read address decoder; and
a matrix of non-volatile memory cells and associated circuits for reading, modifying and erasing data in the memory block, the matrix divided into functionally independent, simultaneously accessible memory banks independently accessible by the write and read address decoders, each of the banks including a set of reference cells;
an address bus;
a data bus; and
an interface block associated with the LPC communication interface and comprising an address block, a data block and a state machine to control the flow of data to and from the memory block over the address bus and data bus;
wherein the data block includes a read data sub-block and a write data sub-block, the read data sub-block and write data sub-block each configured to be selectively enabled by the state machine.
2. The memory device according to claim 1 , wherein the memory block further comprises:
a read address counter block associated with the read address decoder; and a write address counter block associated with the write address decoder.
3. The memory device according to claim 2 , wherein the memory block further comprises:
a read amplifier block associated with the memory matrix; and
a reference cell block associated with each memory bank.
4. The memory device according to claim 3 , wherein the interface block further comprises an address block; and the address bus is branched from the address block to the read address counter block and the write address counter block.
5. The memory device according to claim 2 , wherein the interface block further comprises a state machine to enable one of the read data sub-block and the write data sub-block of the data block based upon read/write operations of the memory matrix.
6. The memory device according to claim 1 , wherein the interface block further comprises a selection block to receive input signals from the LPC interface and generate respective read and write signals for the memory device.
7. A method of making a memory device with a Low Pin Count (LPC) communication interface, the method comprising:
providing a memory block including a matrix of non-volatile memory cells and associated circuits for reading from, writing to, and erasing data on the memory block and write address decoding and read address decoding;
providing an interface block associated with the LPC communication interface to control the flow of data to and from the memory block over an address bus and data bus, including providing a data block comprising a read data sub-block and a write data sub-block, the read data sub-block configured to be selectively enabled when data is read from the memory block and the write data sub-block configured to be selectively enabled when data is written to the memory block; and
dividing the memory matrix into functionally independent, simultaneously accessible memory banks independently accessible by the write and read address decoding circuits, each of said banks including a set of reference cells.
8. The method according to claim 7 , wherein the memory block further comprises:
a read address counter block associated with the read address decoding circuit; and a write address counter block associated with the write address decoding circuit.
9. The method according to claim 8 , wherein the interface block further comprises an address block; and the address bus is branched from the address block to the read address counter block and the write address counter block.
10. The method according to claim 7 , wherein the interface block further comprises a state machine to enable one of the read data sub-block and the write data sub-block of the data block based upon read/write operations of the memory matrix.
11. The method according to claim 7 , wherein the interface block further comprises a selection block to receive input signals from the LPC interface and generate respective read and write signals for the memory device.