Electronic memory device having high integration density non-volatile memory cells and a reduced capacitive coupling
View Patent ↗A flash NAND electronic memory device includes non-volatile cells having a high integration density and a relative programming method. The memory device is integrated on a semiconductor substrate and includes a matrix with word lines and bit lines organized in sectors of memory cells. The memory device is between the cells of the opposite word lines belonging to at least one of the sectors of the matrix. A lateral coating along the direction of the bit lines has at least one conductive layer with a contact terminal being selectively biased or left floating during each program, read or erase operation. Each cell belongs to a sector.
1. An electronic memory device comprising:
a semiconductor substrate;
a plurality of non-volatile memory cells integrated on said semiconductor substrate and organized in a matrix of rows and columns, said matrix of memory cells being divided into a plurality of sectors;
a plurality of word lines connected to the rows of said matrix;
a plurality of bit lines connected to the columns of said matrix; and
a coating between memory cells of opposite word lines belonging to at least one of said plurality of sectors of said matrix, said coating comprising spaced apart conductive layers and at least one contact terminal connected thereto to selectively apply a biasing potential during at least one operation of said plurality of memory cells.
2. An electronic memory device according to claim 1 , wherein the at least one operation includes at least one of program, read and erase operations.
3. An electronic memory device according to claim 1 , wherein said coating laterally extends on said memory cells along a direction of said plurality of bit lines.
4. An electronic memory device according to claim 1 , wherein said coating comprises at least one insulating layer below said spaced apart conductive layers.
5. An electronic memory device according to claim 1 , wherein said plurality of non-volatile memory cells are of a Flash NAND type.
6. An electronic memory device comprising:
a semiconductor substrate;
a plurality of non-volatile memory cells on said semiconductor substrate and organized in a matrix of rows and columns, said matrix of memory cells being divided into a plurality of sectors;
a plurality of word lines connected to the rows of said matrix;
a plurality of bit lines connected to the columns of said matrix;
a coating between memory cells of opposite word lines belonging to at least one of said plurality of sectors of said matrix, said coating comprising spaced apart conductive layers and at least one contact terminal connected thereto; and
a biasing device for selectively applying a first biasing voltage to said at least one contact terminal during program and read operations of said plurality of memory cells and a second biasing voltage to said at least one contact terminal during erase operations of said plurality of memory cells.
7. An electronic memory device according to claim 6 , wherein said coating laterally extends on said memory cells along a direction of said plurality of bit lines.
8. An electronic memory device according to claim 6 , wherein said coating comprises at least one insulating layer below said spaced apart conductive layers.
9. An electronic memory device according to claim 6 , wherein the first biasing voltage is between 0V and 20V during the programming operation.
10. An electronic memory device according to claim 6 , wherein the first biasing voltage is between 0V and 4.5V during the read operation.
11. An electronic memory device according to claim 6 , wherein the second biasing voltage is v-e between 0V and −20V during the read operation.