Method for manufacturing differential isolation structures in a semiconductor electronic device and corresponding structure
View Patent ↗Embodiments of this invention relate to a method for manufacturing isolation structures with different depths in a monolithically integrated semiconductor electronic device. An inventive method according to an embodiment of the invention comprises a first step of defining active areas on a semiconductor material substrate, a second step of forming isolation structures by realising trenches in said substrate and then filling them with field oxide, a third step of defining lithographically at least a first device area, and a fourth step of realising a digging in the substrate and in the field oxide of said first device area.
1. A method comprising:
defining first and second active areas on a semiconductor substrate;
forming first isolation structure around said first active area and a second isolation structure around said second active area by forming trenches in said active areas and subsequently forming field oxide in said trenches;
removing an upper portion of said second isolation structure for said second active area so that the second isolation structure has a height that is lower than the first isolation structure, such that said first and second isolation structures are not substantially coplanar;
forming a floating gate layer; and
wherein removing an upper portion of said second isolation structure includes also removing an upper portion of said second active area while leaving in place a lower portion of said second active area, said upper portion having a thickness equal to said floating gate layer.
2. A method according to claim 1 , wherein said removing includes two successive removal steps.
3. A method according to claim 2 , wherein said two successive removal steps comprise selectively etching said substrate towards said field oxide and etching said field oxide.
4. A method according to claim 3 , including using a BOE etching during etching of said field oxide.
5. A method according to claim 3 , includes providing a diluted HF solution etch of said field oxide.
6. A method according to claim 1 , including removing between 50 and 200 nm.
7. A method according to claim 1 , including removing between 80 and 130 nm.
8. A method according to claim 1 , including forming a sacrificial dielectric within said first device area.
9. A method according to claim 8 , including forming said sacrificial dielectric with a thickness comprised between 10 and 20 nm.
10. A method according to claim 8 , including forming, on said substrate, a succession of one or more dielectric layers comprising a first silicon oxide layer is provided before realizing said digging, wherein said sacrificial dielectric is silicon oxide and it has the same thickness as that of said first silicon oxide.
11. A method according to claim 10 , including removing said sacrificial dielectric and removing a portion of said first silicon oxide layer and simultaneously removing said sacrificial dielectric and a portion of said first silicon oxide layer.
12. A method according to claim 8 , including implanting in said first device area and screening off said implanting step in at least a second device area by means of a first nitride layer.