Circuit and method for testing analog-digital converter
View Patent ↗A circuit for testing an analog-digital converter includes: a subtracter which receives a converted value having a plurality of bits outputted from the analog-digital converter and an expected value having a plurality of bits, the subtracter calculating a difference value having a plurality of bits between the converted value and the expected value; and a logical operation circuit which receives the difference value, the logical operation circuit performing an exclusive-NOR operation between adjacent bits in the plurality of bits constituting the difference value, thereby outputting an exclusive-NOR value having a plurality of bits.
1. A circuit for testing an analog-digital converter, comprising:
a subtracter which receives a converted value having a plurality of bits outputted from the analog-digital converter and an expected value having a plurality of bits, the subtracter calculating a difference value having a plurality of bits between the converted value and the expected value; and
a logical operation circuit which receives the difference value, the logical operation circuit performing an exclusive-NOR operation between adjacent bits in the plurality of bits constituting the difference value, thereby outputting an exclusive-NOR value having a plurality of bits.
2. The circuit according to claim 1 , further comprising:
a logical sum circuit which receives the exclusive-NOR value outputted from the logical operation circuit and a predetermined mask value having a plurality of bits, the logical sum circuit performing a logical sum operation between the exclusive-NOR value and the predetermined mask value, thereby outputting a logical sum value having a plurality of bits; and
a logical product circuit which receives the logical sum value, the logical product circuit performing a logical product operation of the plurality of bits constituting the logical sum value.
3. The circuit according to claim 1 , wherein the expected value is inputted to the subtracter from outside.
4. The circuit according to claim 1 , further comprising an expected value generator which generates the expected value.
5. The circuit according to claim 2 , further comprising a bitmask decoder which generates the predetermined mask value.
6. The circuit according to claim 1 , wherein the logical operation circuit includes a plurality of exclusive-NOR gates.
7. The circuit according to claim 2 , wherein the logical sum circuit includes a plurality of OR gates.
8. The circuit according to claim 1 , further comprising the analog-digital converter to be tested.
9. A method for testing an analog-digital converter, comprising the steps of:
inputting an analog input signal to the analog-digital converter, thereby causing the analog-digital converter to output a converted value having a plurality of bits;
calculating a difference value having a plurality of bits between the converted value outputted from the analog-digital converter and an expected value having a plurality of bits; and
performing an exclusive-NOR operation between adjacent bits in the plurality of bits constituting the difference value, thereby outputting an exclusive-NOR value having a plurality of bits.
10. The method according to claim 9 , further comprising the steps of:
performing a logical sum operation between the exclusive-NOR value and a predetermined mask value having a plurality of bits, thereby outputting a logical sum value having a plurality of bits; and
performing a logical product operation of the plurality of bits constituting the logical sum value.
11. The method according to claim 9 , wherein the analog input signal inputted to the analog-digital converter is constant.
12. The method according to claim 9 , wherein the analog input signal inputted to the analog-digital converter increases or decreases step by step.