IP Library Granted Patent US 8,404,496
Granted Patent B2
US 8,404,496 · App. 11/439,119 · Granted Mar 26, 2013

Method of testing a semiconductor device and suctioning a semiconductor device in the wafer state

Inventors: Shigeyuki Maruyama (Kawasaki, JP); Yasuyuki Itoh (Kawasaki, JP); Tetsurou Honda (Kawasaki, JP); Kazuhiro Tashiro (Kawasaki, JP); Makoto Haseyama (Kawasaki, JP); Kenichi Nagashige (Kawasaki, JP); Yoshiyuki Yoneda (Kawasaki, JP); Hirohisa Matsuki (Kawasaki, JP)
Assignee: Fujitsu Semiconductor Limited
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Quick Facts
Patent No.
US 8,404,496
App. No.
11/439,119
Granted
Mar 26, 2013
Kind
B2
Abstract

A semiconductor device has an alignment mark which can be recognized by a conventional wafer prober. A redistribution layer connects electrodes of the semiconductor device to electrode pads located in predetermined positions of the redistribution layer. Metal posts configured to be provided with external connection electrodes are formed on the electrode pads of the redistribution layer. A mark member made of the same material as the metal posts is formed on the redistribution layer. The mark member serves as an alignment mark located in a predetermined positional relationship with the metal posts.

Claims (8)

1. A method of testing semiconductor devices, comprising the steps of:

forming a redistribution layer on the semiconductor devices in a wafer state;

forming a seal resin layer on the redistribution layer so as to encapsulate the semiconductor devices;

forming grooves in the seal resin layer along scribe lines by removing portions of the seal resin after encapsulating the semiconductor devices by the seal resin layer, the grooves extending through the seal resin layer so that an entire bottom of each of the grooves reaches the wafer and the wafer surface is exposed in the entire bottom of each of the grooves;

performing a test on the semiconductor devices in the wafer state while recognizing the wafer exposed at an intersection of the grooves as a reference position; and

separating the wafer into individual semiconductor devices by cutting the wafer along the scribe lines,

wherein the forming grooves includes forming the grooves by a dicing saw to have a depth exceeding a thickness of the seal resin layer.

2. The method as claimed in claim 1 , wherein the step of forming grooves includes the step of forming grooves along scribe lines selected from all of the scribe lines provided for the wafer.

Assignments (3)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 27, 2015
From: FUJITSU SEMICONDUCTOR LIMITED
To: SOCIONEXT INC.
Reel/Frame 035508/0637 →
CHANGE OF NAME Recorded Jul 9, 2010
From: FUJITSU MICROELECTRONICS LIMITED
To: FUJITSU SEMICONDUCTOR LIMITED
Reel/Frame 024651/0744 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 9, 2008
From: FUJITSU LIMITED
To: FUJITSU MICROELECTRONICS LIMITED
Reel/Frame 021976/0089 →
Priority Claims (1)
JP 11-321590 · Nov 11, 1999 · national
Continuity (2)
Division 09577932 · May 25, 2000
Related Publication 20060279003A1 · Dec 14, 2006