Prescaler and buffer
A prescaler that operates in a broad band. The prescaler includes a buffer and a counter. The buffer includes a first amplification circuit, which has three inverter circuits of different drive capacities, a second amplification circuit, which has four series-connected inverter circuits, and a feedback circuit. One of the inverter circuits is connected between a capacitor and an inverter circuit via a first switch circuit and a second switch circuit. This varies the drive capacity of the first amplification circuit. The feedback circuit functions as a variable resistor having two transistors.
1. A prescaler comprising:
a buffer including a first amplification circuit which amplifies an input signal and generates an output signal, with the first amplification circuit having a variable drive capacity, and a feedback circuit which feeds back the output signal of the first amplification circuit to the first amplification circuit, with the feedback circuit having a variable resistance; and
a frequency divider which divides the output signal by a predetermined frequency dividing ratio to generate a divisional signal;
the first amplification circuit including:
a plurality of inverter circuits each having an input terminal and an output terminal, with the inverter circuits having different drive capacities; and
a selection circuit coupled to the inverter circuits and the feedback circuit;
wherein the selection circuit includes:
a first switch circuit, coupled to the input terminal of each of the inverter circuits, for selecting one of the inverter circuits in response to a control signal, with the inverter circuits including one or more inverter circuits coupled to ground via the first switch circuit and the inverter circuit selected by the first switch circuit; and
a second switch circuit, coupled to the output terminal of each of the inverter circuits, for coupling the inverter circuit selected by the first switch circuit to the feedback circuit in response to the control signal and discoupling the one or more inverter circuits from the feedback circuit.
2. The prescaler according to claim 1 , wherein the buffer sets the feedback circuit to have a constant resistance and varies the drive capacity of the first amplification circuit.
3. The prescaler according to claim 1 , wherein the buffer further includes a second amplification circuit coupled between the first amplification circuit and the frequency divider, with the second amplification circuit receiving the output signal of the first amplification circuit and providing the output signal to the frequency divider.
4. The prescaler according to claim 3 , wherein the second amplification circuit includes a plurality of series-coupled inverter circuits.
5. The prescaler according to claim 1 , wherein:
the first amplification circuit includes an input terminal for receiving the input signal and an output terminal for outputting the output signal; and
the feedback circuit includes at least one MOS transistor coupled between the output terminal and input terminal of the first amplification circuit.
6. The prescaler according to claim 1 , wherein:
the feedback circuit includes:
a first transistor having a first gate; and
a second transistor coupled in parallel to the first transistor and having a second gate;
the prescaler further comprising:
a voltage generation circuit for generating a first gate voltage supplied to the first gate and a second gate voltage supplied to the second gate.
7. The prescaler according to claim 6 , wherein:
the first amplification circuit varies the drive capacity in response to the control signal; and
the voltage generation circuit generates the first gate voltage and the second gate voltage to vary a resistance of the feedback circuit in response to the control signal.
8. A prescaler for frequency-dividing an input signal and generating a divisional signal, the prescaler comprising:
a buffer for amplifying the input signal and generating an output signal; and
a frequency divider for dividing the output signal of the buffer by a predetermined frequency dividing ratio and generating the divisional signal;
the buffer including:
a first amplification circuit for receiving the input signal and generating the output signal from the input signal, with the first amplification circuit having a variable drive capacity; and
a feedback circuit, coupled to the first amplification circuit, for feeding back the output signal of the first amplification circuit to the first amplification circuit,
wherein the first amplification circuit includes a plurality of inverter circuits having different drive capacities, with the inverter circuits each having an input terminal and an output terminal, and a selection circuit coupled to inverter circuits and the feedback circuit, the selection circuit including:
a first switch circuit, coupled to the input terminal of each of the inverter circuits, for selecting one of the inverter circuits in response to a control signal, with the inverter circuits including one or more inverter circuits coupled to ground via the first switch circuit and the inverter circuit selected by the first switch circuit; and
a second switch circuit, coupled to the output terminal of each of the inverter circuits, for coupling the inverter circuit selected by the first switch circuit to the feedback circuit in response to the control signal and discoupling the one or more inverter circuits from the feedback circuit.
9. A buffer comprising:
a first amplification circuit which amplifies an input signal and generates an output signal, with the first amplification circuit having a variable drive capacity; and
a feedback circuit which feeds back the output signal of the first amplification circuit to the first amplification circuit, with the feedback circuit having a variable resistance;
the first amplification circuit including:
a plurality of inverter circuits each having an input terminal and an output terminal, with the inverter circuits having different drive capacities; and
a selection circuit coupled to the inverter circuits and the feedback
wherein the selection circuit includes:
a first switch circuit, coupled to the input terminal of each of the inverter circuits, for selecting one of the inverter circuits in response to a control signal, with the inverter circuits including one or more inverter circuits coupled to ground via the first switch circuit and the selected inverter circuit; and
a second switch circuit, coupled to the output terminal of each of the inverter circuits, for coupling the selected inverter circuit to the feedback circuit in response to the control signal and discoupling the one or more inverter circuits from the feedback circuit.
10. The buffer according to claim 9 , further comprising:
a second amplification circuit, coupled to the first amplification circuit and the feedback circuit, for amplifying the output signal of the first amplification circuit.
11. The buffer according to claim 9 , wherein:
the first amplification circuit includes an input terminal for receiving the input signal and an output terminal for outputting the output signal; and
the feedback circuit includes at least one MOS transistor coupled between the output terminal and input terminal of the first amplification circuit.
12. The buffer according to claim 9 , wherein the feedback circuit includes:
a first transistor having a first gate; and
a second transistor coupled in parallel to the first transistor and having a second gate, the first and second transistors being controlled by separate gate voltages respectively supplied to the first and second gates.