IP Library Granted Patent US 7,528,468
Granted Patent B2
US 7,528,468 · App. 11/526,971 · Granted May 5, 2009

Capacitor assembly with shielded connections and method for forming the same

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Quick Facts
Patent No.
US 7,528,468
App. No.
11/526,971
Granted
May 5, 2009
Kind
B2
Abstract

A capacitor assembly ( 82 ) is formed on a substrate ( 20 ). The capacitor assembly a first conductive plate ( 38 ) and a second conductive plate ( 60 ) formed over the substrate such that the second conductive plate is separated from the first conductive plate by a distance. A conductive trace ( 40 ) is formed over the substrate that is connected to the first conductive plate and extends away from the capacitor assembly. A conductive shield ( 62 ) is formed over at least a portion of the conductive trace that is separated from the first and second conductive plates to control a fringe capacitance between the second conductive plate and the conductive trace.

Claims (38)

1. A microelectronic assembly comprising:

a substrate;

a first conductive plate formed over the substrate;

a second conductive plate formed over the substrate such that the second conductive plate is separated from the first conductive plate by a distance, the first and second conductive plates jointly forming a capacitor;

a conductive trace formed over the substrate being connected to the first conductive plate and extending away from the capacitor; and

a conductive shield formed over at least a portion of the conductive trace and being separated from the first and second conductive plates to control a fringe capacitance between the second conductive plate and the conductive trace.

2. The microelectronic assembly of claim 1 , wherein at least a portion of the conductive shield is positioned between the second conductive plate and the conductive trace and the conductive shield is formed over at least 50% of the conductive trace.

3. The microelectronic assembly of claim 2 , further comprising at least one semiconductor device formed over the substrate, the conductive trace interconnecting the first conductive plate and the at least one semiconductor device.

4. The microelectronic assembly of claim 3 , wherein at least a portion of the second conductive plate is moveable between first and second positions such that the distance between the first and second conductive plates is a first distance when the second conductive plate is in the first position and a second distance when the second conductive plate is in the second position.

5. The microelectronic assembly of claim 4 , further comprising a second conductive trace formed over the substrate interconnecting the second conductive plate and the at least one semiconductor device.

6. The microelectronic assembly of claim 5 , wherein the second conductive plate is formed over the first conductive trace such that the first conductive plate is positioned between the substrate and the second conductive plate and the conductive shield is formed over the conductive trace such that the conductive trace is positioned between the substrate and the conductive shield.

7. The microelectronic assembly of claim 6 , wherein a gap is defined between the conductive shield and the second conductive plate and further comprising first and second conductive shield members formed on opposing sides of the conductive trace adjacent to the gap, the conductive shield members being electrically connected to the conductive shield.

8. The microelectronic assembly of claim 7 , further comprising an electrically insulating material between the conductive trace and the conductive shield and within the gap between the conductive shield and the second conductive plate.

9. The microelectronic assembly of claim 8 , wherein the second conductive plate comprises at least one side wall member extending therefrom around a periphery of the first conductive plate such that a cavity is formed above and on opposing sides of the first conductive plate between the first conductive plate and the second conductive plate, the at least one side wall member having an opening therethough, the conductive trace extending through the opening, and further comprising an electrically insulating body between the conductive trace and the at least one side wall member.

10. The microelectronic assembly of claim 7 , wherein the at least one semiconductor device comprises an integrated circuit formed over the substrate, the integrated circuit being configured to generate a signal representative of a first capacitance when the second conductive plate is in the first position and a second capacitance when the second conductive plate is in the second position.

11. A capacitive pressure sensor comprising:

a substrate;

a first conductive plate formed over the substrate;

a second conductive plate formed over the substrate and the first conductive plate such that the second conductive plate is moveable between first and second positions, the first and second conductive plates jointly forming a capacitor and being separated by a first distance when the second conductive plate is in the first position and being separated by a second distance when the second plate is in the second position;

a first conductive trace formed over the substrate having first and second portions, the first portion of the first conductive trace being connected to the first conductive plate;

a second conductive trace formed over the substrate having first and second portions, the first portion of the second conductive trace being connected to the second conductive plate;

an integrated circuit formed over the substrate being connected to the second portion of the first conductive trace and the second portion of the second conductive trace such that the integrated circuit is electrically coupled to the first and second conductive plates, the integrated circuit being configured to generate a signal representative of a first capacitance when the second conductive plate is in the first position and a second capacitance when the second conductive plate is in the second position; and

a conductive shield formed over at least a portion of the first conductive trace being electrically separated from the first and second conductive plates to control a fringe capacitance between the second conductive plate and the first conductive trace.

12. The capacitive pressure sensor of claim 11 , wherein the second conductive plate and the conductive shield comprise a selected material.

13. The capacitive pressure sensor of claim 12 , wherein the first conductive trace further comprises a third portion interconnecting the first and second portions of the first conductive trace, a gap is defined between the conductive shield and the second conductive plate adjacent to the third portion first conductive trace, the first portion of the first conductive trace is positioned between the substrate and the second conductive plate, and the conductive shield covers substantially all of the second portion of the first conductive trace.

14. The capacitive pressure sensor of claim 13 , further comprising an electrically insulating material between the first conductive trace and the conductive shield and within the gap between the conductive shield and the second conductive plate, and wherein the second conductive plate comprises at least one side wall member extending therefrom around a periphery of the first conductive plate such that a cavity is formed above and on opposing sides of the first conductive plate between the first conductive plate and the second conductive plate, the at least one side wall member having an opening therethough, the conductive trace extending through the opening, and further comprising an electrically insulating body between the conductive trace and the at least one side wall member.

15. The capacitive pressure sensor of claim 14 , further comprising first and second conductive shield members formed on opposing sides of the first conductive trace adjacent to the gap, the conductive shield members being electrically connected to the conductive shield and separated from the first conductive trace.

16. A microelectronic assembly comprising:

a substrate;

at least one semiconductor device formed over the substrate;

a first conductive plate formed over the substrate;

a second conductive plate formed over the substrate such that the second conductive plate is separated from the first conductive plate by a distance, the first and second conductive plates jointly forming a capacitor;

a conductive trace formed over the substrate, the conductive trace interconnecting the first conductive plate and the at least one semiconductor device and extending away from the capacitor; and

a conductive shield formed over at least a portion of the conductive trace and being separated from the first and second conductive plates to control a fringe capacitance between the second conductive plate and the conductive trace, at least a portion of the conductive shield being positioned between the second conductive plate and the conductive trace.

17. The microelectronic assembly of claim 16 , wherein at least a portion of the second conductive plate is moveable between first and second positions such that the distance between the first and second conductive plates is a first distance when the second conductive plate is in the first position and a second distance when the second conductive plate is in the second position.

18. The microelectronic assembly of claim 17 , wherein the at least one semiconductor device comprises an integrated circuit formed over the substrate, the integrated circuit being configured to generate a signal representative of a first capacitance when the second conductive plate is in the first position and a second capacitance when the second conductive plate is in the second position.

19. The microelectronic assembly of claim 16 , wherein a gap is defined between the conductive shield and the second conductive plate and further comprising first and second conductive shield members formed on opposing sides of the conductive trace adjacent to the gap, the conductive shield members being electrically connected to the conductive shield.

20. The microelectronic assembly of claim 19 , further comprising an electrically insulating material between the conductive trace and the conductive shield and within the gap between the conductive shield and the second conductive plate.

Assignments (20)
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040925 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Feb 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V. F/K/A FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 052917/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040928 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Jan 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 052915/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 037486 FRAME 0517. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS. Recorded Dec 10, 2019
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 053547/0421 →
CORRECTIVE ASSIGNMENT TO CORRECT THE TO CORRECT THE APPLICATION NO. FROM 13,883,290 TO 13,833,290 PREVIOUSLY RECORDED ON REEL 041703 FRAME 0536. ASSIGNOR(S) HEREBY CONFIRMS THE THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS.. Recorded Feb 20, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: SHENZHEN XINGUODU TECHNOLOGY CO., LTD.
Reel/Frame 048734/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE PATENTS 8108266 AND 8062324 AND REPLACE THEM WITH 6108266 AND 8060324 PREVIOUSLY RECORDED ON REEL 037518 FRAME 0292. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS. Recorded Feb 1, 2017
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 041703/0536 →
RELEASE OF SECURITY INTEREST Recorded Nov 7, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 040928/0001 →
RELEASE OF SECURITY INTEREST Recorded Sep 21, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V., F/K/A FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 040925/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 4, 2016
From: FREESCALE SEMICONDUCTOR, INC.
To: NORTH STAR INNOVATIONS INC.
Reel/Frame 037694/0264 →
ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS Recorded Jan 13, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 037518/0292 →
ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS Recorded Jan 12, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 037486/0517 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037354/0225 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037354/0823 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037356/0143 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037356/0553 →
SECURITY AGREEMENT Recorded Nov 6, 2013
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 031591/0266 →
SECURITY AGREEMENT Recorded Jun 18, 2013
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 030633/0424 →
SECURITY AGREEMENT Recorded May 13, 2010
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS COLLATERAL AGENT
Reel/Frame 024397/0001 →
SECURITY AGREEMENT Recorded Sep 23, 2009
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A.
Reel/Frame 023273/0099 →
SECURITY AGREEMENT Recorded Feb 2, 2007
From: FREESCALE SEMICONDUCTOR, INC.; FREESCALE ACQUISITION CORPORATION; FREESCALE ACQUISITION HOLDINGS CORP.; FREESCALE HOLDINGS (BERMUDA) III, LTD.
To: CITIBANK, N.A. AS COLLATERAL AGENT
Reel/Frame 018855/0129 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 25, 2006
From: MCNEIL, ANDREW C.; BILIC, DUBRAVKA; HOOPER, STEPHEN R.
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 018348/0912 →