Nanocrystal non-volatile memory cell and method therefor
View Patent ↗A method of forming a semiconductor device includes forming a first dielectric layer over a semiconductor substrate, forming a plurality of discrete storage elements over the first dielectric layer, thermally oxidizing the plurality of discrete storage elements to form a second dielectrics over the plurality of discrete storage elements, and forming a gate electrode over the second dielectric layer, wherein a significant portion of the gate electrode is between pairs of the plurality of discrete storage elements. In one embodiment, portions of the gate electrode is in the spaces between the discrete storage elements and extends to more than half of the depth of the spaces.
1. A method of forming a semiconductor device, the method comprising:
forming a first dielectric layer over a semiconductor substrate;
forming a plurality of discrete storage elements over the first dielectric layer;
thermally oxidizing the plurality of discrete storage elements to form a second dielectric layer over the plurality of discrete storage elements; and
forming a gate electrode over the second dielectric layer, wherein a portion of the gate electrode extends below a height of the plurality of discrete storage elements is thereby between adjacent pairs of the plurality of discrete storage elements.
2. The method of claim 1 , wherein thermally oxidizing the plurality of discrete storage elements to form the second dielectric layer further comprises increasing a thickness of the first dielectric layer.
3. The method of claim 1 , further comprising:
forming a layer comprising nitride over the first dielectric layer prior to forming the plurality of discrete storage elements, wherein forming the plurality of discrete storage elements further comprise forming the plurality of discrete storage elements over the layer comprising nitride; and
forming a third dielectric layer over the second dielectric layer.
4. The method of claim 3 , wherein forming the plurality of discrete storage elements comprises forming the plurality of discrete storage elements, wherein the discrete storage elements are hemispherical.
5. The method of claim 3 , wherein forming the plurality of discrete storage elements comprises forming the plurality of discrete storage elements, wherein the discrete storage elements are spherical.
6. The method of claim 3 , wherein:
forming the first dielectric layer comprises forming a tunnel dielectric; and
thermally oxidizing to from the second dielectric layer comprises forming a nitrided oxide layer on each of the plurality of discrete storage elements.
7. The method of claim 3 , wherein:
forming the third dielectric layer is further characterized by the third dielectric layer being part of a control dielectric.
8. The method of claim 7 , wherein forming the third dielectric layer is further characterized by the third dielectric having a tor surface with a contour that follows the plurality of discrete storage elements.
9. A method of forming a semiconductor device, the method comprising:
forming a first discrete storage element and a second discrete storage element over a semiconductor substrate, wherein:
the first discrete storage element and the second discrete storage element are separated by a space; and
the space has a depth; and
forming a first portion of a gate electrode within the space and over the first and second discrete storage elements, wherein the first portion extends within the space more than half of the depth.
10. The method of claim 9 , further comprising:
forming a first dielectric layer over the semiconductor substrate, wherein the first discrete storage element and the second discrete storage element are formed over the first dielectric layer; and
thermally oxidizing the first and second discrete storage elements to form a second dielectric layer of nitrided oxide over the first and second discrete storage elements.
11. The method of claim 10 , wherein the step of thermally oxidizing the first and second discrete storage elements to form the second dielectric layer further comprises increasing a thickness of the first dielectric layer.
12. The method of claim 10 , further comprising:
forming a nitrided layer over the first dielectric layer prior to forming the first and second discrete storage elements, wherein forming the first and second discrete storage elements further comprises forming the plurality of discrete storage elements over the nitrided layer; and
forming a third dielectric layer over the second dielectric layer.
13. The method of claim 9 , wherein forming a first portion of the gate electrode further comprises forming the first portion of the gate electrode, wherein the first portion fills the space.