NANOCRYSTAL NON-VOLATILE MEMORY CELL AND METHOD THEREFOR
A method of forming a semiconductor device, which is preferably a memory cell, includes forming a first dielectric layer over a semiconductor substrate, forming a plurality of discrete storage elements over the first dielectric layer, wherein each of the plurality of discrete storage elements has a diameter value that is approximately equal to each other, and forming a second dielectric layer over the plurality of discrete storage elements, wherein the second dielectric layer has a thickness, wherein the ratio of the thickness of the second dielectric to the diameter value is less than approximately 0.8. The spacing between the plurality of discrete storage elements may be greater than or equal to approximately the thickness of the second dielectric layer.
1 . A method of forming a semiconductor device, the method comprising:
forming a first dielectric layer over a semiconductor substrate;
forming a plurality of discrete storage elements over the first dielectric layer, wherein each of the plurality of discrete storage elements has a diameter value that is approximately equal to each other; and
forming a second dielectric layer over the plurality of discrete storage elements, wherein the second dielectric layer has a thickness, wherein the ratio of the thickness of the second dielectric to the diameter value is less than approximately 0.8.
2 . The method of claim 1 , wherein forming the second dielectric layer comprises thermally oxidizing the plurality of discrete storage elements.
3 . The method of claim 1 , further comprising forming a passivation around each of the plurality of discrete storage elements.
4 . The method of claim 1 , wherein forming the plurality of discrete storage elements further comprises forming the plurality of discrete storage elements, forming a space between two discrete storage elements of the plurality of discrete storage elements and the space is greater than or equal to approximately the thickness of the second dielectric layer.
5 . The method of claim 1 , further comprising:
forming a gate electrode over the second dielectric layer, wherein the second dielectric layer is a control dielectric; and
forming source regions and drain regions adjacent the gate electrode and within the semiconductor substrate.
6 . The method of claim 1 , wherein forming the first dielectric layer further comprises forming a tunnel dielectric.
7 . The method of claim 1 , wherein forming the plurality of discrete storage elements comprises forming the plurality of discrete storage elements, wherein the plurality of discrete storage elements is substantially spherical.
8 . A semiconductor device comprising:
a semiconductor substrate;
a first dielectric layer over a semiconductor substrate;
a plurality of discrete storage elements over the first dielectric layer, wherein at least a majority of the plurality of discrete storage elements have a diameter value that is approximately equal to each other; and
a second dielectric layer over the plurality of discrete storage elements, wherein the second dielectric layer has a thickness, wherein the ratio of the thickness of the second dielectric layer to the diameter value is less than approximately 0.8.
9 . The semiconductor device of claim 8 , wherein the first dielectric layer is a tunnel dielectric and the second dielectric layer is a control dielectric.
10 . The semiconductor device of claim 9 , wherein the diameter value is greater than or equal to approximately 12 nanometers.
11 . The semiconductor device of claim 10 , wherein the discrete storage elements comprise storage elements selected from the group consisting of nanocrystals and nanorods.
12 . The semiconductor device of claim 10 , further comprising:
a gate electrode over the second dielectric layer;
a source region adjacent the gate electrode; and
a drain region adjacent the gate electrode.
13 . The semiconductor device of claim 8 , wherein spaces exist between pairs of discrete storage elements of the plurality of discrete storage elements and the majority of the spaces is greater than or equal to approximately the thickness of the second dielectric layer.
14 . The semiconductor device of claim 8 , wherein the plurality of discrete storage elements are substantially spherical.
15 . The semiconductor device of claim 8 , wherein at least a majority of the plurality discrete storage elements is substantially all of the plurality of discrete storage elements.
16 . A method of forming a semiconductor device, the method comprising:
forming a tunnel dielectric over a semiconductor substrate;
forming a plurality of discrete storage elements over the tunnel dielectric layer, wherein:
at least a majority of the plurality of discrete storage elements each have a diameter value that is approximately equal to each other and each are spaced apart from each other a distance that is approximately equal to each other;
forming a control dielectric over the plurality of discrete storage elements, wherein the control dielectric has a thickness, wherein the diameter value is greater than or equal to the thickness of the control dielectric and the distance is greater than or equal to the thickness of the control dielectric.
17 . The method of claim 16 , wherein forming the control dielectric further comprises forming the control dielectric, wherein a ratio of the thickness of the control dielectric to the diameter value is less than approximately 0.8.
18 . The method of claim 17 , wherein forming the control dielectric comprises thermally oxidizing the plurality of discrete storage elements.
19 . The method of claim 17 , further comprising forming a passivation around each of the plurality of discrete storage elements.
20 . The method of claim 16 , wherein forming the plurality of discrete storage elements comprising forming the plurality of discrete storage elements, wherein the plurality of discrete storage elements is spheres.