IP Library Granted Patent US 7,697,518
Granted Patent B1
US 7,697,518 · App. 11/532,225 · Granted Apr 13, 2010

Integrated search engine devices and methods of updating same using node splitting and merging operations

Assignee: Netlogic Microsystems, Inc.
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Quick Facts
Patent No.
US 7,697,518
App. No.
11/532,225
Granted
Apr 13, 2010
Kind
B1
Abstract

Methods of updating b-tree data structures (e.g., b*tree data structure) using search key insertion and deletion operations proceed from respective known states (e.g., respective canonical forms). These insertion operations include inserting a first search key into the b-tree by reconfiguring (e.g., pre-processing) a plurality of sibling nodes of the b-tree into a predetermined overloaded form having a shape that is independent of a value of the first search key to be inserted therein. An operation is then performed to split the sibling nodes by redistributing the first and other search keys among an expanded plurality of the sibling nodes. These insertion operations use a process that trades off possibly performing additional memory accesses (e.g., to shift search keys (and/or handles or pointers) to the predetermined overloaded form) for the certainty that the same key movements are ultimately performed during operations to split sibling nodes.

Claims (9)

1. A method of updating a b-tree of search keys within a search engine, comprising the steps of:

inserting a first search key into the b-tree by reconfiguring a plurality of sibling nodes of the b-tree into an overloaded form having a shape that is independent of a value of the first search key inserted therein and then performing a split operation on the plurality of sibling nodes by redistributing the first and other search keys among an expanded plurality of the sibling nodes; and

deleting a second search key from the b-tree by reconfiguring the plurality of sibling nodes into a predetermined underloaded form having a shape that is independent of a value of the second search key omitted therefrom and then performing a merge operation on the plurality of sibling nodes by redistributing remaining search keys among a reduced plurality of the sibling nodes.

2. The method of claim 1 , wherein the b-tree is a b*tree of type N−(N+1), where N is a positive integer greater than one; and wherein the predetermined underloaded form includes a sibling node at a minimum fill level less one.

3. The method of claim 1 , wherein the overloaded form is a canonical form.

4. An integrated circuit search engine, comprising:

a hardware implemented b-tree of search keys; and

a maintenance engine electrically coupled to said hardware implemented b-tree of search keys, said maintenance engine configured to insert a first search key into the b-tree by reconfiguring a plurality of sibling nodes of the b-tree into an overloaded form having a shape that is independent of a value of the first search key inserted therein and then performing a split operation on the plurality of sibling nodes by redistributing the first and other search keys among an expanded plurality of the sibling nodes, wherein said maintenance engine is further configured to delete a second search key from the b-tree by reconfiguring the plurality of sibling nodes into a predetermined underloaded form having a shape that is independent of a value of the second search key omitted therefrom and then performing a merge operation on the plurality of sibling nodes by redistributing remaining search keys among a reduced plurality of the sibling nodes.

5. The integrated circuit search engine of claim 4 , wherein the overloaded form is a canonical form.

Assignments (12)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 22, 2021
From: USHIWATA, TAKAMI; NISHI, HAJIME; ANDO, IKUMI; HONDA, YUKI
To: HITACHI METALS, LTD.
Reel/Frame 058181/0486 →
CORRECTIVE ASSIGNMENT TO CORRECT THE EXECUTION DATE OF THE MERGER PREVIOUSLY RECORDED ON REEL 047642 FRAME 0417. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT, Recorded Mar 6, 2019
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 048521/0395 →
MERGER Recorded Oct 5, 2018
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 047642/0417 →
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENTS Recorded Feb 3, 2017
From: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
To: BROADCOM CORPORATION
Reel/Frame 041712/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 1, 2017
From: BROADCOM CORPORATION
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 041706/0001 →
PATENT SECURITY AGREEMENT Recorded Feb 11, 2016
From: BROADCOM CORPORATION
To: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
Reel/Frame 037806/0001 →
CHANGE OF NAME Recorded Apr 16, 2015
From: NETLOGIC MICROSYSTEMS, INC.
To: NETLOGIC I LLC
Reel/Frame 035443/0824 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 16, 2015
From: NETLOGIC I LLC
To: BROADCOM CORPORATION
Reel/Frame 035443/0763 →
RELEASE OF SECURITY INTEREST Recorded Aug 30, 2011
From: SILICON VALLEY BANK
To: NETLOGIC MICROSYSTEMS, INC.; NETLOGIC MICROSYSTEMS INTERNATIONAL LIMITED; NETLOGIC MICROSYSTEMS CAYMANS LIMITED
Reel/Frame 026830/0141 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 23, 2009
From: INTEGRATED DEVICE TECHNOLOGY, INC.
To: NETLOGIC MICROSYSTEMS, INC.
Reel/Frame 022996/0786 →
SECURITY AGREEMENT Recorded Jul 17, 2009
From: NETLOGIC MICROSYSTEMS, INC.; NETLOGIC MICROSYSTEMS INTERNATIONAL LIMITED; NETLOGIC MICROSYSTEMS CAYMANS LIMITED
To: SILICON VALLEY BANK
Reel/Frame 022973/0710 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 15, 2006
From: DE WIT, PASCAL
To: INTEGRATED DEVICE TECHNOLOGY, INC.
Reel/Frame 018261/0699 →