Performance variation compensating circuit and method
View Patent ↗A circuit's performance may vary based on various factors such as, for example, process, voltage, and/or temperature. In one embodiment, a circuit includes an input terminal which receives an input signal, a delay selection section which delays the input signal by a delay amount selected by a performance variation indicator, an impedance selection section which outputs the delayed input signal as a compensated delayed signal, where the impedance selection section uses a driver impedance amount selected by the performance variation indicator, and an output terminal which outputs the compensated delayed signal. The circuit may also include a ring oscillator, a frequency counter which provides a count value which indicates a number of rising edges of an output of the ring oscillator which occur during a period of a reference frequency, and a decoder which uses the count value to output the performance variation indicator.
1. A circuit comprising:
a ring oscillator;
a frequency counter coupled to the ring oscillator, the frequency counter providing a count value which indicates a number of edges of predetermined direction of an output of the ring oscillator which occur during a period of a reference frequency;
a decoder coupled to the frequency counter and which uses the count value to output a performance variation indicator, the performance variation indicator indicating a variation in at least one characteristic selected from a group consisting of process, voltage, and temperature, the decoder determining a difference between an actual count value and a minimum count value of the counter and dividing the difference by a total number of delay elements and driver circuits presently selected by the performance variation indicator;
an input terminal which receives an input signal;
a delay selection section coupled to the input terminal and which delays the input signal by a delay amount selected by the performance variation indicator to provide a delayed input signal;
an impedance selection section coupled to the delay selection section and which outputs the delayed input signal as a compensated delayed signal, the impedance selection section using a driver impedance amount selected by the performance variation indicator; and
an output terminal coupled to the impedance selection section and which outputs the compensated delayed signal.
2. The circuit of claim 1 , wherein when the performance variation indicator has a first value a first delay amount is indicated and a first driver impedance amount is indicated, and when the performance variation indicator has as a second value a second delay amount is indicated and a second driver impedance is indicated, wherein at least one of the first delay amount and first driver impedance amount is different from the second delay amount and the second driver impedance, respectively.
3. The circuit of claim 1 , wherein the decoder further comprises a circuit for subtracting two values and for dividing, wherein the minimum count value is proportional to a frequency of the ring oscillator.
4. The circuit of claim 3 , wherein the delay selection section further comprises a plurality of delay elements coupled in parallel and the impedance selection section further comprises a plurality of driver circuits coupled in parallel.
5. The circuit of claim 1 , wherein the delay selection section comprises a plurality of delay paths, wherein each delay path of the plurality of delay paths is enabled or not enabled in response to the performance variation indicator to provide the delay amount selected.
6. The circuit of claim 5 , wherein only one of the plurality of delay paths is enabled in response to the performance variation indicator.
7. The circuit of claim 1 , wherein the impedance selection section comprises a plurality of driver circuits coupled in parallel, wherein each of the driver circuits is enabled or not enabled in response to the performance variation indicator to provide the driver impedance amount selected.
8. A method comprising:
receiving a ring oscillator frequency signal;
receiving a reference frequency signal;
providing a count value which indicates at least a number of rising or falling pulse edges of the ring oscillator frequency signal which occur during a period of a reference frequency signal;
using the count value to provide a performance variation indicator, the performance variation indicator indicating a variation in at least one characteristic selected from a group consisting of process, voltage, and temperature, wherein the performance variation indicator is provided by determining a difference between the count value and a minimum count value and dividing the difference by a total number of both delay elements used to provide a delay amount and driver circuits providing the driver impedance presently selected by the performance variation indicator;
receiving an input signal;
delaying the input signal by the delay amount in response to the performance variation indicator to provide a delayed signal; and
modifying a driver impedance used to drive the delayed signal to an output terminal, said modifying determined in response to the performance variation indicator to provide a compensated delayed signal.
9. The method of claim 8 , wherein the performance variation indicator represents a variation in at least one characteristic selected from a group consisting of process, voltage, and temperature.
10. The method of claim 8 , wherein the delaying the input signal comprises:
using the performance variation indicator to select one of a plurality of delay paths for delaying the input signal.
11. The method of claim 8 , wherein the modifying the driver impedance further comprises:
using the performance variation indicator to select at least one of a plurality of driver circuits to provide the compensated delayed signal, wherein the plurality of driver circuits are coupled in parallel.
12. The method of claim 8 , wherein the minimum count value is either a measured count value, an assumed count value or a simulated count value.
13. A circuit comprising:
a ring oscillator which provides a ring oscillator frequency signal;
a frequency counter coupled to the ring oscillator, the frequency counter provides a count value which indicates a number of rising edges of the ring oscillator frequency signal which occur during a period of a reference frequency signal;
an AND gate for receiving the ring oscillator frequency signal as a first input and a signal derived from the reference frequency signal as a second input, and providing an output to an increment input of the frequency counter;
a PVT decoder, coupled to the frequency counter, which uses the count value to output a PVT control signal which represents PVT variations;
an input terminal which receives an input signal;
a delay selection section which delays the input signal by a delay amount selected by the PVT control signal to provide a delayed input signal; and
an impedance selection section which outputs the delayed input signal as a compensated delayed signal, the impedance selection section using a driver impedance amount selected by the PVT control signal.
14. The circuit of claim 13 , wherein the delay selection section further comprises a plurality of delay elements coupled in parallel between a first node and a second node, each of the plurality of delay elements implementing a different amount of delay.
15. The circuit of claim 13 , wherein the PVT decoder further comprises:
a frequency-based calculation circuit which provides a calculation value using the count value; and
a latch which latches the calculation value to provide the PVT control signal.
16. The circuit of claim 13 , further comprising:
a control signal generator which receives the reference frequency signal, and in response to the reference frequency signal, provides the signal to the second input of the AND gate, provides a reset signal to the frequency counter and provides an enable signal to the latch.
17. The circuit of claim 13 , wherein the delay selection section comprises a plurality of delay paths, wherein each delay path of the plurality of delay paths is enabled or not enabled in response to the PVT control signal to provide the delay amount selected.
18. The circuit of claim 13 , wherein the impedance selection section comprises a plurality of driver circuits coupled in parallel, wherein each of the driver circuits is enabled or not enabled in response to the PVT control signal to provide the driver impedance amount selected.