Source side injection storage device with spacer gates and method therefor
View Patent ↗A storage device structure ( 10 ) has two bits of storage per control gate ( 34 ) and uses source side injection (SSI) to provide lower programming current. A control gate ( 34 ) overlies a drain electrode formed by a doped region ( 22 ) that is positioned in a semiconductor substrate ( 12 ). Two select gates ( 49 and 50 ) are implemented with conductive sidewall spacers adjacent to and lateral to the control gate ( 34 ). A source doped region ( 60 ) is positioned in the semiconductor substrate ( 12 ) adjacent to one of the select gates for providing a source of electrons to be injected into a storage layer ( 42 ) underlying the control gate. Lower programming results from the SSI method of programming and a compact memory cell size exists.
1. A storage device structure comprising:
a substrate;
a first doped region in the substrate;
a second doped region in the substrate;
a first storage layer overlying the first doped region;
a second storage layer overlying the second doped region;
a first control gate over the first storage layer and having a first sidewall and a second sidewall;
a second control gate over the second storage layer and having a first sidewall and a second sidewall,
a first select gate on the first sidewall of the first control gate;
a second select gate on the second sidewall of the first control gate;
a third select gate on the first sidewall of the second control gate;
a fourth select gate on the second sidewall of the second control gate; and
a third doped region in the substrate between the second and third select gates.
2. The storage device structure of claim 1 further comprising:
a metal layer overlying the first and second control gates and the third doped region; and
a contact between the third doped region and the metal layer.
3. The storage device structure of claim 2 , further comprising:
a dielectric layer over the first and second control gates; and
a contact opening through the dielectric layer to the third doped region.
4. The storage device structure of claim 1 , wherein the first and second storage layers comprise nanoclusters.
5. The storage device structure of claim 1 , wherein the first, second, third, and fourth select gates comprise polysilicon.
6. The storage device structure of claim 1 , wherein the substrate is of a first conductivity type and the first, second, and third doped regions are of a second conductivity type.
7. The storage device structure of claim 1 , wherein the third doped region is substantially aligned to the second and third select gates.
8. The storage device structure of claim 1 , wherein the third doped region extends slightly under the second and third select gates.
9. A storage device structure comprising:
a substrate;
a first doped region in the substrate;
a second doped region in the substrate;
a first nitride film storage layer overlying the first doped region;
a second nitride film storage layer overlying the second doped region;
a first control gate over the first nitride film storage layer and having a first sidewall and a second sidewall;
a second control gate over the second nitride film storage layer and having a first sidewall and a second sidewall;
a first select gate on the first sidewall of the first control gate;
a second select gate on the second sidewall of the first control gate;
a third select gate on the first sidewall of the second control gate;
a fourth select gate on the second sidewall of the second control gate; and
a third doped region in the substrate between the second and third select gates.
10. The storage device structure of claim 9 further comprising:
a metal layer overlying the first and second control gates and the third doped region; and
a contact between the third doped region and the metal layer.
11. The storage device structure of claim 9 , further comprising:
a dielectric layer over the first and second control gates; and
a contact opening through the dielectric layer to the third doped region.
12. The storage device structure of claim 9 , wherein the first, second, third, and fourth select gates comprise polysilicon.
13. The storage device structure of claim 9 , wherein the substrate is of a first conductivity type and the first, second, and third doped regions are of a second conductivity type.
14. The storage device structure of claim 9 , wherein the third doped region is substantially aligned to the second and third select gates.
15. The storage device structure of claim 9 , wherein the third doped region extends slightly under the second and third select gates.
16. A storage device structure comprising:
a substrate;
a first doped region in the substrate;
a second doped region in the substrate;
a first storage layer overlying the first doped region;
a second storage layer overlying the second doped region;
a first control gate over the first storage layer and having a first sidewall and a second sidewall;
a second control gate over the second storage layer and having a first sidewall and a second sidewall;
an insulating liner surrounding the first control gate and the second control gate;
a first select gate on the insulating liner adjacent the first sidewall of the first control gate;
a second select gate on the insulating liner adjacent the second sidewall of the first control gate;
a third select gate on the insulating liner adjacent the first sidewall of the second control gate;
a fourth select gate on the insulating liner and adjacent the second sidewall of the second control gate; and
a third doped region in the substrate between the second and third select gates.
17. The storage device structure of claim 16 further comprising:
a metal layer overlying the first and second control gates and the third doped region; and
a contact between the third doped region and the metal layer.
18. The storage device structure of claim 16 , further comprising:
a dielectric layer over the first and second control gates; and
a contact opening through the dielectric layer to the third doped region.
19. The storage device structure of claim 16 , wherein the third doped region is substantially aligned to the second and third select gates.
20. The storage device structure of claim 16 , wherein the third doped region extends slightly under the second and third select gates.