Dynamic branch prediction using a wake value to enable low power mode for a predicted number of instruction fetches between a branch and a subsequent branch
View Patent ↗A processor has a fetch unit and a branch execution unit. The fetch unit has a branch predictor. The branch predictor has a branch target buffer and a branch direction predictor. A wake value is a number of instruction fetches that is predicted to be performed after a fetch of a branch. Thus, for a first branch, for example, a first wake number is predicted. A low power mode of the branch predictor is enabled for a duration of the first wake value in response to hit in the branch target buffer in which the hit is in response to the first branch.
1. A method, comprising:
providing a processor wherein the processor comprises a fetch unit and a branch execution unit, wherein the fetch unit comprises a branch predictor, wherein the branch predictor comprises a wake table, a branch target buffer, and a branch direction predictor, wherein the branch target buffer comprises a memory coupled to the wake table;
predicting a wake number that is a number of instruction fetches performed after a fetch of a first branch, wherein the wake table stores the wake number at an index of a fetch address that immediately follows a fetch address of the first branch; and
enabling a low power mode of the branch predictor for a duration of the wake number in response to a hit in the branch target buffer in response to the first branch.
2. The method of claim 1 , wherein the step of enabling the low power mode comprises disabling read enables.
3. The method of claim 1 , wherein the step of providing comprises:
providing the processor wherein the processor comprises the fetch unit and the branch execution unit, wherein the fetch unit comprises the branch predictor, wherein the branch predictor comprises the branch target buffer and the branch direction predictor, wherein the memory has a plurality of entries, wherein each entry has a valid field, a TAG field, and a target address field.
4. The method of claim 1 , wherein the step of predicting the wake number is further characterized by subtracting an address of a target of the first branch from an address of a second branch, in which no branches occur between the first branch and the second branch.
5. The method of claim 4 , wherein the step of predicting the wake number further comprises providing a previous branch register for storing the address of the first branch during execution of the first branch and storing the address of the second branch in response to execution of the second branch.
6. A method, comprising:
providing a processor having a branch predictor, wherein the branch predictor comprises a branch target buffer and a wake table, the branch target buffer stores target addresses of branches, and the branch predictor has a low power mode;
storing a wake number in the wake table corresponding to a predicted number of fetches between a first branch and an immediately following branch, wherein the wake number is stored in the wake table at an index of a fetch address that immediately follows a fetch address of the first branch; and
enabling the low power mode of the branch target buffer for the wake number of fetches in response to the branch target buffer have a hit in response to the first branch.
7. The method of claim 6 , further comprising calculating the wake number based on a next fetch address immediately following an address of the first branch and an address of the immediately following branch.
8. The method of claim 7 , wherein the step of providing comprises:
providing the processor having the branch predictor, wherein the branch predictor comprises the branch target buffer, the branch target buffer stores target addresses of branches, and the branch predictor has a low power mode, wherein the branch target buffer comprises a memory coupled to the wake table, wherein the memory stores the target addresses of branches.
9. A processor comprising:
a fetch unit, implemented at least partially in hardware, comprising:
a branch predictor having a branch target buffer that stores target addresses of branches and having a wake table coupled to the branch target buffer that stores a plurality of wake values, wherein:
each wake value is representative of a predicted number of fetches between a corresponding branch and an immediately following branch and each wake value is stored in the wake table at an index of a fetch address that immediately follows a fetch address of the corresponding branch,
the branch predictor has a low power mode that is enabled in response to a hit in the branch target buffer caused by a branch; and
the low power mode is for a duration of a wake value of the plurality of wake numbers that corresponds to the branch that caused the hit;
a branch execution unit, implemented at least partially in hardware, coupled to the fetch unit.
10. The processor of claim 9 , wherein the branch execution unit provides the plurality of wake values to the branch predictor by calculating a difference in addresses between a target of a branch and an immediately following branch.