Automated wear leveling in non-volatile storage systems
Methods and apparatus for performing wear leveling in a non-volatile memory system are disclosed. Included is a method for performing wear leveling in a memory system that includes a first zone, which has a first memory element that includes contents, and a second zone includes identifying the first memory element and associating the contents of the first memory element with the second zone while disassociating the contents of the first memory element from the first zone. In one embodiment, associating the contents of the first memory element with the second involves moving contents of a second memory element into a third memory element, then copying the contents of the first memory element into the second memory element.
1. A memory system comprising:
a plurality of units of erasable and re-programmable non-volatile memory cells having contiguous physical addresses organized into zones with address boundaries therebetween and wherein a distinct range of logical addresses are mapped into each of the zones; and
a memory controller that reassigns the boundary addresses to delete at least one unit from each of the zones and to add said at least one unit to an adjacent zone without changing the number of units in the individual zones, the memory controller subsequently accessing the zones for programming data to or reading data from the reassigned memory cell units therein according to logical addresses of the data, and the memory controller repetitively reassigning the boundary addresses and accessing the zones at least until the plurality of memory cell units have all been moved from their zones to adjacent zones, thereby to spread out usage of the units accessed through the logical addresses;
wherein reassigning the boundary addresses includes deleting a number of units from each of the zones less than ten percent of the units within the zone and adding said number of units to an adjacent zone.
2. The memory system of claim 1 , wherein the zones are formed with portions of their memory cell units in an individual plurality of memory planes, and wherein reassigning the boundary addresses includes deleting at least one unit from each portion of the zones in each of the memory planes and adding said at least one unit to an adjacent portion of another zone within the same plane.
3. The memory system of claim 1 , wherein the memory cell units individually include a plurality of simultaneously erasable memory cells.
4. The memory system of claim 3 , wherein the memory cell units individually include a plurality of pages that are individually programmable with data.
5. The memory system of claim 1 , wherein reassigning the boundary addresses includes copying any data stored in said at least one unit from each of the zones into the added unit of the adjacent zone.
6. A memory system comprising:
a memory array having a plurality of zones individually including a plurality of units of re-programmable non-volatile memory cells that are erasable together, wherein a distinct range of logical addresses received by the memory system are mapped into the individual zones; and
circuitry that receives a logical address within the distinct logical address range of one of the zones, and converts the received logical address into a physical address of at least one of the plurality of memory cell erase units within said one zone that tends to even out a number of usage cycles of erasing and re-programming the erase units within said one zone;
wherein the converted address represented less than ten percent of the distinct logical address range of said one of the zones.
7. The memory system of claim 6 , wherein converting the logical address into the physical address includes reference to a table of corresponding logical and physical addresses, and which additionally comprises changing the correspondence between logical and physical erase unit addresses in order to tend to even out the frequency of use of the erase units within said one zone.
8. The memory system of claim 6 , wherein changing the correspondence between logical and physical erase unit addresses includes swapping physical addresses of the erase units within said one zone that have a highest and a lowest accumulated number of usage cycles.
9. The memory system of claim 6 , wherein the memory cells have a target endurance limit of a maximum number of usage cycles that the memory cells are to experience, and wherein changing the correspondence between logical and physical erase unit addresses occurs prior to the number of usage cycles of an erase unit whose corresponding address is changed reaching said target maximum number.