Array quad flat no-lead package and method of forming same
An array QFN package ( 10 ) includes a first semiconductor package ( 12 ) and a lead frame ( 14 ) having a plurality of leads ( 16 ). A first IC die ( 22 ) is attached on a first side to the first semiconductor package ( 12 ) and is electrically connected to the leads ( 16 ) of the lead frame ( 14 ). A mold compound ( 30 ) encapsulates the first IC die ( 22 ), a portion of the first semiconductor package ( 12 ) and a portion of the leads ( 16 ) such that a plurality of I/O terminals ( 32 ) on the semiconductor package ( 10 ) is exposed.
1. A method of forming a semiconductor package, the method comprising:
attaching a first side of a first semiconductor package to a lead frame having a plurality of leads;
attaching a first IC die to a second side of the first semiconductor package;
electrically connecting the first IC die to the leads of the lead frame; and
performing a molding operation to encapsulate the first IC die, a portion of the first semiconductor package and a portion of the leads.
2. The method of forming a semiconductor package of claim 1 , further comprising attaching a second IC die to the first IC die and electrically connecting the second IC die to the leads of the lead frame.
3. The method of forming a semiconductor package of claim 2 , wherein the second IC die is electrically connected to the leads of the lead frame via a plurality of wire bonded wires.
4. The method of forming a semiconductor package of claim 1 , further comprising removing a tape from the semiconductor package to expose a plurality of I/O terminals on the semiconductor package.
5. The method of forming a semiconductor package of claim 1 , wherein the step of attaching the first semiconductor package to the lead frame comprises scrubbing the first side of the first semiconductor package against a package receiving area of the lead frame.
6. The method of forming a semiconductor package of claim 1 , wherein the first semiconductor package is one of a wire bond package and a flip chip package.
7. The method of forming a semiconductor package of claim 1 , wherein the first IC die is electrically connected to the leads of the lead frame via a plurality of wire bonded wires.
8. The method of forming a semiconductor package of claim 1 , wherein the first IC die is attached to the second side of the first semiconductor package with a die attach epoxy.
9. A method of forming a plurality of semiconductor packages, the method comprising:
attaching first sides of respective first semiconductor packages to a lead frame having a plurality of leads;
attaching a plurality of first IC dice to second sides of the respective first semiconductor packages;
electrically connecting the first IC dice to the leads of the lead frame; and
performing a molding operation to encapsulate the first IC dice, a portion of the first semiconductor packages and a portion of the leads.
10. The method of forming a plurality of semiconductor packages of claim 9 , further comprising attaching a plurality of second IC dice to respective ones of the first IC dice and electrically connecting the second IC dice to the leads of the lead frame.
11. The method of forming a plurality of semiconductor packages of claim 10 , wherein the second IC dice are electrically connected to the leads of the lead frame via a plurality of wire bonded wires.
12. The method of forming a plurality of semiconductor packages of claim 9 , further comprising removing a tape from the semiconductor packages to expose a plurality of I/O terminals on the semiconductor packages.
13. The method of forming a plurality of semiconductor packages of claim 9 , further comprising performing a singulating operation to separate adjacent ones of the semiconductor packages.
14. The method of forming a plurality of semiconductor packages of claim 9 , wherein the step of attaching the first semiconductor packages to the lead frame comprises scrubbing the first sides of the first semiconductor packages against respective package receiving areas of the lead frame.
15. The method of forming a plurality of semiconductor packages of claim 9 , wherein the first semiconductor packages is one or a combination of wire bond packages and flip chip packages.
16. The method of forming a plurality of semiconductor packages of claim 9 , wherein the first IC dice are electrically connected to the leads of the lead frame via a plurality of wire bonded wires.