Circuit arrangement and method of operating such circuit arrangement
View Patent ↗In order to provide a circuit arrangement ( 100; 100′; 100″ ) for use in a data transmission system comprising at least one input stage (IS) being connected downstream of at least one bus system (CB), in particular of at least one C[ontroller]A[rea]N[etwork] bus system, the input stage (IS) comprising at least one resistive ladder (RL) for dividing the input signals; and at least one amplifier stage (AS) connected downstream of the input stage (IS), as well as a corresponding method with improved common mode range and with better H[igh]F[requency] performance, it is proposed that that the voltage range of the amplifier stage (AS) is limitated to a defined maximum voltage, in particular to the supply voltage (VCC).
1. Circuit arrangement for use in a data transmission system, the circuit arrangement comprising:
at least one input stage being connected downstream of at least one bus system, in particular of at least one C[ontroller]A[rea]N[etwork] bus system, the input stage comprising at least one resistive ladder for dividing the input signals, wherein the resistive ladder comprises two parallel resistor branches; and
at least one amplifier stage connected downstream of the input stage, characterized in that the voltage range of the amplifier stage is limited to a defined maximum voltage, in particular to the supply voltage, wherein the input stage further comprises a divided bus system connected downstream of the resistive ladder, characterized in that the resistive ladder comprises at least six resistors determining the recessive level of the high branch of the bus system as well as the low branch of the bus system, in particular with
the high branch of the divided bus system being connected between the first resistor and the second resistor,
the high branch of the bus system being connected between the second resistor and the third resistor,
the low branch of the divided bus system being connected between the fourth resistor and the fifth resistor,
the low branch of the bus system being connected between the fifth resistor and the sixth resistor,
the first resistor and the fourth resistor being connected on ground potential, and
the third resistor and the sixth resistor being connected on supply voltage.
2. Circuit arrangement according to claim 1 , characterized in that the resistive ladder is terminated to ground potential.
3. Circuit arrangement according to claim 2 , characterized in that the resistive ladder is defined by at least one division factor constituted by a serial alignment of at least one resistor arrangement and at least one resistor.
4. Circuit arrangement according to claim 1 , wherein the input stage further comprises a divided bus system connected downstream of the resistive ladder, characterized in that the amplifier stage comprises:
at least one pair of transistors assigned to the high branch of the divided bus system as well as
at least one pair of transistors assigned to the low branch of the divided bus system.
5. Circuit arrangement according to claim 4 , characterized in
that the respective emitter terminal of the at least two transistors is connected to the high branch or to the low branch of the divided bus system via at least one respective reference resistor,
that the collector terminal of the first transistor is assigned to the high branch of the divided bus system,
that the collector terminal of the second transistor is assigned to the low branch of the divided bus system,
that the collector terminal of the first transistor assigned to the high branch of the divided bus system is connected with the base terminal of the first transistor assigned to the high branch of the divided bus system,
that the base terminal of the first transistor assigned to the high branch of the divided bus system is connected with the base terminal of the second transistor assigned to the high branch of the divided bus system,
that the collector terminal of the second transistor assigned to the low branch of the divided bus system is connected with the base terminal of the second transistor assigned to the low branch of the divided bus system, and
that the base terminal of the first transistor assigned to the low branch of the divided bus system is connected with the base terminal of the second transistor assigned to the low branch of the divided bus system.
6. System base chip, comprising at least one circuit arrangement according to claim 1 and covering C[ontroller]A[rea]N[etwork] applications and L[ocal]l[nterconnect]N[etwork] applications, ranging from local electric window nodes to central engine management and dashboard applications.
7. Circuit arrangement according to claim 1 , wherein one resistor branch of the two parallel resistor branches comprises the first resistor, the second resistor, and the third resistor, and wherein another resistor branch of the two parallel resistor branches comprises the fourth resistor, the fifth resistor, and the sixth resistor.
8. Circuit arrangement for use in a data transmission system, the circuit arrangement comprising:
at least one input stage being connected downstream of at least one bus system, in particular of at least one C[ontroller]A[rea]N[etwork] bus system, the input stage comprising at least one resistive ladder for dividing the input signals, wherein the resistive ladder comprises two parallel resistor branches; and
at least one amplifier stage connected downstream of the input stage, characterized in that the voltage range of the amplifier stage is limited to a defined maximum voltage, in particular to the supply voltage, wherein the input stage further comprises a divided bus system connected downstream of the resistive ladder, characterized in that the amplifier stage comprises:
at least one pair of transistors assigned to the high branch of the divided bus system as well as
at least one pair of transistors assigned to the low branch of the divided bus system, characterized in
that the respective emitter terminal of the at least two transistors is connected to the high branch or to the low branch of the divided bus system via at least one respective reference resistor,
that the collector terminal of the first transistor is assigned to the high branch of the divided bus system,
that the collector terminal of the second transistor is assigned to the low branch of the divided bus system,
that the collector terminal of the first transistor assigned to the high branch of the divided bus system is connected with the base terminal of the first transistor assigned to the high branch of the divided bus system,
that the base terminal of the first transistor assigned to the high branch of the divided bus system is connected with the base terminal of the second transistor assigned to the high branch of the divided bus system,
that the collector terminal of the second transistor assigned to the low branch of the divided bus system is connected with the base terminal of the second transistor assigned to the low branch of the divided bus system, and
that the base terminal of the first transistor assigned to the low branch of the divided bus system is connected with the base terminal of the second transistor assigned to the low branch of the divided bus system.
9. Circuit arrangement according to claim 8 , characterized in that the resistive ladder is terminated to ground potential.
10. Circuit arrangement according to claim 9 , characterized in that the resistive ladder is defined by at least one division factor constituted by a serial alignment of at least one resistor arrangement and at least one resistor.
11. Circuit arrangement according to claim 8 , wherein the input stage further comprises a divided bus system connected downstream of the resistive ladder, characterized in that the resistive ladder comprises at least six resistors determining the recessive level of the high branch of the bus system as well as the low branch of the bus system, in particular with
the high branch of the divided bus system being connected between the first resistor and the second resistor,
the high branch of the bus system being connected between the second resistor and the third resistor,
the low branch of the divided bus system being connected between the fourth resistor and the fifth resistor,
the low branch of the bus system being connected between the fifth resistor and the sixth resistor,
the first resistor and the fourth resistor being connected on ground potential, and
the third resistor and the sixth resistor being connected on supply voltage.
12. System base chip, comprising at least one circuit arrangement according to claim 8 and covering C[ontroller]A[rea]N[etwork] applications and L[ocal]l[nterconnect]N[etwork] applications, ranging from local electric window nodes to central engine management and dashboard applications.