Circuit design system and circuit design program

1. A circuit design system comprising:

a storage unit in which a netlist is stored;

a fault-candidate extracting module configured to extract equivalent fault class G 1 to G I (I is an integer equal to or greater than 1) from said netlist and to generate a fault-candidate data indicating said equivalent fault class G i (i is an integer not less than 1 and not greater than I), wherein said equivalent fault class G i is a portion of a design target circuit in which a fault position can not be specified by an external measurement and includes a plurality of nodes N i1 to N iji (J i is a number of nodes included in said equivalent fault class G i );

a judgment module configured to select a target node out of said plurality of nodes N i1 to N iji included in said equivalent fault class G i indicated by said fault-candidate data, wherein at least one observation point used for failure analysis is inserted into said target node; and

an observation-point inserting module configured to update said netlist by inserting said at least one observation point into said target node,

wherein said judgment module decides said target node based on said number J i ,

a probability that a fault is included in said equivalent fault class G i is represented by P i , a parameter D i with respect to said equivalent fault class G i is given by the following equation: D i =J i ×P i , and a sum of said parameter D i with respect to all equivalent fault class is represented by M,

said judgment module decides said target node such that said sum M is reduced due to said insertion of said observation point,

a reduction rate of said sum M due to said insertion of said observation point takes a maximum value.

2. The circuit design system according to claim 1 ,

wherein said judgment module selects said target node out of said plurality of nodes N i1 to N iji included in one equivalent fault class G i that has a maximum parameter D i among said equivalent fault class G 1 to G I .

3. The circuit design system according to claim 2 ,

wherein said one equivalent fault class G i is divided into a first equivalent fault class G i−1 and a second equivalent fault class G i−2 due to said insertion of said observation point,

wherein said judgment module decides said target node such that said parameter D i−1 with respect to said first equivalent fault class G i−1 becomes closest to said parameter D i−2 with respect to said second equivalent fault class G i−2 .

4. The circuit design system according to claim 1 ,

wherein said judgment module selects said target node out of said plurality of nodes N i1 to N iji included in one equivalent fault class G i that has a maximum number J i among said equivalent fault class G 1 to G I .

5. The circuit design system according to claim 1 ,

wherein said judgment module selects said target node out of said plurality of nodes N i1 to N iji included in one equivalent fault class G i that has a maximum interconnection length among said equivalent fault class G 1 to G I .

6. The circuit design system according to claim 1 ,

wherein interconnection lengths of respective of said plurality of nodes N i1 to N iJi are represented by L i1 to L iJi ,

wherein said judgment module calculates said probability P i as a value that depends on a sum of said interconnection lengths L i1 to L iJi of said equivalent fault class G i .

7. The circuit design system according to claim 1 ,

wherein said judgment module calculates said probability P i as a value that depends on said number J i of said equivalent fault class G i .

8. The circuit design system according to claim 1 , further comprising: a layout module configured to determine a layout of said design target circuit with reference to said netlist and to generate a layout data indicating said layout,

wherein said judgment module refers to said layout data and said fault-candidate data to calculate parameter S 1i to S Ki respective of which indicate amounts of structures X 1 to X K (K is an integer equal to or greater than 1) in said equivalent fault class G i , and calculates said probability P i based on said parameter S ki (k is an integer not less than 1 and not greater than K)

9. The circuit design system according to claim 1 , further comprising a diagnosis-tree generating module configured to generate a diagnosis-tree data indicating a diagnosis-tree of said design target circuit by using said netlist and test patterns,

wherein said fault-candidate extracting module extracts said equivalent fault class G 1 to G I from said netlist by referring to said diagnosis-tree data.

10. The circuit design system according to claim 1 ,

wherein said design target circuit is designed based on a physical synthesis method.

11. The circuit design system according to claim 10 , further comprising:

a logic synthesis module configured to generate a partial netlist by performing a logic synthesis of a RTL description of a part of said design target circuit and to store said partial netlist as said netlist in said storage unit;

a placing module configured to place cells included in said part of design target circuit with reference to said partial netlist and to generate a placement data indicating placement of said cells; and

a distance extracting module configured to extract an intercell distance based on said placement data and to generate a distance data indicating said intercell distance,

wherein interconnection lengths of respective of said plurality of nodes N i1 to N iJi are represented by L i1 to L iJi ,

wherein said judgment module sets interconnection length L iJ (j is an integer not less than 1 and not greater than J i ) to said inter-cell distance by referring to said distance data, and calculates said probability P i as a value that depends on a sum of said interconnection lengths L i1 to L iJi of said equivalent fault class G i .

12. The circuit design system according to claim 1 ,

wherein said target node is electrically connected to an external output terminal.

13. A computer readable recording medium with a computer program recorded thereon comprising code that, when executed, causes a computer to perform a circuit design procedures comprising:

(A) reading a netlist out of a storage unit;

(B) extracting equivalent fault class G 1 to G I (I is an integer equal to or greater than 1) from said netlist, wherein said equivalent fault class G i (i is an integer not less than 1 and not greater than I) is a portion of a design target circuit in which a fault position can not be specified by an external measurement and includes a plurality of nodes N i1 to N iJi (J is a number of nodes included in said equivalent fault class G i );

(C) selecting a target node out of said plurality of nodes N i1 to N iJi included in said equivalent fault class G i , wherein at least one observation point used for failure analysis is inserted into said target node; and

(D) updating said netlist by inserting said at least one observation point into said target node,

wherein in said (C) step, said target node is decided based on said number J i ,

a probability that a fault is included in said equivalent fault class G i is represented by P i , a parameter D i with respect to said equivalent fault class G i is given by the following equation: D i =J i ×P i , and a sum of said parameter D i with respect to all equivalent fault class is represented by M,

said (C) step includes: deciding said target node such that said sum M is reduced due to said insertion of said observation point, a reduction rate of said sum M due to said insertion of said observation point takes a maximum value.

14. The computer readable recording medium according to claim 13 ,

wherein in said (C) step, said target node is selected out of said plurality of nodes N i1 to N iJi included in one equivalent fault class G i that has a maximum parameter D i among said equivalent fault class G 1 to G I .

15. The computer readable recording medium according to claim 13 ,

wherein in said (C) step, said target node is selected out of said plurality of nodes N i1 to N iJi included in one equivalent fault class G i that has a maximum number J i among said equivalent fault class G 1 to G I .

16. The computer readable recording medium according to claim 13 ,

wherein in said (C) step, said target node is selected out of said plurality of nodes N i1 to N iJi included in one equivalent fault class G i that has a maximum interconnection length among said equivalent fault class G 1 to G I .