Field effect transistor having contact plugs in the source region greater than in the drain region
View Patent ↗A semiconductor device having a field effect transistor formed on a semiconductor layer on an insulator, comprising: a drain electrode wiring formed over a drain region of the field effect transistor; a source electrode wiring formed over a source region of the field effect transistor; first contact plugs connecting the drain region and the drain electrode wiring; and second contact plugs which connect the source region and the source electrode wiring, and the number of which is greater than the first contact plugs.
1. A semiconductor device having a field effect transistor formed on a semiconductor layer on an insulator, comprising:
a drain electrode wiring formed over a drain region of the field effect transistor;
a source electrode wiring formed over a source region of the field effect transistor;
first contact plugs connecting the drain region and the drain electrode wiring; and
second contact plugs which connect the source region and the source electrode wiring, and the number of which is greater than the first contact plugs.
2. The semiconductor device according to claim 1 , wherein the number of the second contact plugs are formed to be twice or more the number of the first contact plugs.
3. The semiconductor device according to claim 1 , wherein the source electrode wiring is formed over substantially the entire surface of the source region.
4. The semiconductor device according to claim 1 , wherein the source region is formed so as to surround the drain region.
5. The semiconductor device according to claim 4 , wherein the field effect transistor further has a substantially ring-shaped gate electrode interposed between the source region and the drain region.
6. The semiconductor device according to claim 4 , wherein the field effect transistor further has a substantially U-shaped gate electrode interposed between the source region and the drain region.
7. The semiconductor device according to claim 4 , wherein the field effect transistor further has a substantially L-shaped gate electrode interposed between the source region and the drain region.
8. The semiconductor device according to claim 1 , wherein the field effect transistor further has a gate electrode formed into a substantially rectangular shape,
the source region has a gate adjacent section adjacent to the gate electrode and an extending section extending in the direction of gate width of the gate electrode, and the second contact plugs are formed in the gate adjacent section and the extending section.
9. The semiconductor device according to claim 1 , wherein the source electrode wiring is a source electrode wiring common to a plurality of circuit blocks.
10. The semiconductor device according to claim 9 , wherein the source electrode wiring is interposed between the circuit blocks.
11. The semiconductor device according to claim 1 , wherein a plurality of recesses, protrusions, cutout portions or notches are formed in the surface of the source electrode wiring.
12. The semiconductor device according to claim 1 , wherein the source electrode wiring is connected to power supply wiring or ground wiring.
13. The semiconductor device according to claim 1 , wherein the field effect transistor constitutes an oscillating circuit, PLL circuit or reference voltage generating circuit, analog-digital signal conversion circuit or digital-analog signal conversion circuit.
14. The semiconductor device according to claim 1 , wherein a portion of the drain region and the source region of the field effect transistor are in contact with the insulator.
15. The semiconductor device according to claim 1 , wherein the field effect transistor is a Fin field effect transistor.
16. A semiconductor device having a plurality of field effect transistors formed on a semiconductor layer on an insulator, comprising:
a first drain electrode wiring formed over a drain region of a first transistor;
a second drain electrode wiring formed over a drain region of a second transistor;
a source region formed common to the first and second transistors;
a source electrode wiring formed over the source region;
first contact plugs connecting the drain region of the first transistor and the first drain electrode wiring;
second contact plugs connecting the drain region of the second transistor and the second drain electrode wiring; and
third contact plugs which connect the source region and the source electrode wiring, and the number of which is greater than the sum of the first contact plugs and the second contact plugs.
17. The semiconductor device according to claim 16 , wherein the source region is also formed common to a source region of another transistor differing from the first and second transistors.
18. The semiconductor device according to claim 16 , wherein the source electrode wiring is connected to power supply wiring or ground wiring.
19. The semiconductor device according to claim 16 , wherein the field effect transistor constitutes an oscillating circuit, PLL circuit or reference voltage generating circuit, analog-digital signal conversion circuit or digital-analog signal conversion circuit.