Planar dual gate semiconductor device
A method of fabricating a dual-gate semiconductor device is provided in which silicidation of the source and drain contact regions ( 34, 36 ) is carried out after the first gate ( 12 ) is formed on part of a first surface ( 14 ) of a silicon body ( 16 ) but before forming a second gate ( 52 ) on a second surface ( 44 ) of the silicon body which is opposite the first surface. The first gate ( 12 ) serves as a mask to ensure that the silicided source and drain contact regions are aligned with the silicon channel ( 18 ). Moreover, by carrying out the silicidation at an early stage in the fabrication, the choice of material for the second gate is not limited by any high-temperature processes. Advantageously, the difference in material properties at the second surface of the silicon body resulting from silicidation enables the second gate to be aligned laterally between the silicide source and drain contact regions.
1. A method of fabricating a dual-gate semiconductor device having a silicon body which comprises a channel and source and drain contact regions separated laterally by the channel, the method comprising the steps of:
forming a first gate on part of a first surface of a silicon body, thereby defining a channel in the silicon body under the first gate;
siliciding regions of the silicon body not covered by the first gate, so as to define silicide source and drain contact regions and then,
forming a second gate on a second surface of the silicon body which is opposite the first surface, wherein the second gate is aligned laterally between the silicide source and drain contact regions.
2. A method according to claim 1 , further comprising the step of:
forming a recess in the second surface between the silicide source and drain contact regions before the second gate is formed, wherein the second gate is formed in the recess.
3. A method according to claim 2 , wherein the recess is formed by selectively etching, from the second surface, a portion of the silicon between the silicide source and drain contact regions.
4. A method according to claim 3 , further comprising the step of:
oxidising the second surface before selectively etching.
5. A method according claim 2 , further comprising the step of:
forming at least one insulating spacer within the recess before forming the second gate to prevent contact between the second gate and the silicide source and/or drain contact regions.
6. A method according to claim 1 , wherein the second surface of the silicon body is initially bonded to an insulating layer which is supported by a first substrate.
7. A method according to claim 6 , further comprising the steps of:
bonding a second substrate to the first gate and the first surface of the silicon body after the silicide source and drain contact regions are defined; and then,
removing the first substrate and the insulating layer so as to expose the second surface of the silicon body.
8. A method according to claim 1 , further comprising the steps of:
forming at least one spacer adjacent the first gate on the first surface ( 14 ); and then,
implanting dopant through an exposed part of the first surface so as to define junction regions adjacent the channel before the silicide source and drain contact regions are defined.
9. A method according to claim 1 , wherein the siliciding includes the steps of:
depositing a metal layer over the first surface;
annealing the metal layer so as to form silicide source and drain contact regions thereunder; and then,
removing the metal layer from the first surface.