Method of low voltage programming of non-volatile memory cells
View Patent ↗A low voltage method of programming a selected non-volatile memory cell in a memory array having a gate node coupled to a wordline WL(n) and a drain node connected to a selected bitline by injecting hot carriers from a drain region of an injecting memory cell having a gate node coupled to a next neighbor wordline WL(n−1) into a floating gate of the selected non-volatile memory cell on the wordline WL(n).
1. A low voltage method of programming a selected non-volatile memory cell in a memory array having a gate node coupled to a wordline WL(n) and a drain node connected to a selected bitline, comprising:
(a) injecting hot carriers from a drain region of an injecting memory cell having a gate node coupled to a next neighbor wordline WL(n−1) into a floating gate of the selected non-volatile memory cell on the wordline WL(n), including:
applying a high passing voltage V passH to all unselected wordlines except for the next neighbor word line WL(n−1);
applying V pgm to the selected word line WL(n); and
linearly sweeping a next neighbor word line WL(n−1) gate node voltage from about 0 V to about a V read .
2. A low voltage method of programming a non-volatile memory cell as recited in claim 1 , further comprising:
(b) determining a threshold voltage of the selected non-volatile memory cell; and
(c) locking out the non-volatile memory cell if the threshold voltage is greater than a target threshold voltage.
3. A low voltage method of programming a selected non-volatile memory cell in a memory array having a gate node coupled to a wordline WL(n) and a drain node connected to a selected bitline, comprising:
(a) injecting hot carriers from a drain region of an injecting memory cell having a gate node coupled to a next neighbor wordline WL(n−1) into a floating gate of the selected non-volatile memory cell on the wordline WL(n);
(b) deter mining a threshold voltage of the selected non-volatile memory cell; and
(c) locking out the non-volatile memory cell if the threshold voltage is greater than a target threshold voltage,
wherein, when the threshold voltage is less than the target voltage, further comprising:
holding the selected bitline at ground;
applying V dd to all unselected bitlines;
applying low passing voltage V passL to a drain gate select (SGD) line;
applying V pp to common source line;
applying a high passing voltage V passH to all unselected wordlines except for the next neighbor word line WL(n−1);
applying the high passing voltage V passH to a source gate select (SGS) line;
applying V pgm to the selected word line WL(n); and
sweeping a next neighbor word line WL(n−1) gate node voltage from about 0 V to about a V read .
4. A low voltage method as recited in claim 3 , further comprising:
incrementing the program voltage V pgm and the V passH and V passL voltages; and returning to determining (b).
5. A low voltage method as recited in claim 3 , wherein V pgm ranges from about 8V to about 14V, V passL ranges from about 4V to about 10V, V passH ranges from about 5V to about 10V, V pp ranges from about 3.5V to about 5.5V, and V dd ranges from about 1.8V to about 3.6V.
6. A low voltage method of programming as recited in claim 2 when the threshold voltage is less than the target voltage, further comprising:
holding the selected bitline at V pp ;
grounding to all unselected bitlines;
applying high passing voltage V passH to SGD line and unselected wordlines except for the next neighbor wordline WL(n−1);
applying low passing voltage V passL to SGS line;
grounding common source line;
applying V pgm to the selected word line WL{n); and
sweeping a next neighbor word line WL(n−1) gate node voltage from about 0 V to about a V read .
7. A low voltage method as recited in claim 5 , further comprising:
incrementing the program voltage V pgm and the V passH and V passL voltages; and
returning to determining (b).
8. A low voltage method as recited in claim 6 , wherein V pgm ranges from about 8V to about 14V, V passL ranges from about 4V to about 10V, V passH ranges from about 5V to about 10V, V pp ranges from about 3.5V to about 5.5V, and V dd ranges from about 1.8V to about 3.6V.
9. A low voltage method as recited in claim 1 , wherein the memory array is a NAND type memory array.
10. A low voltage method of programming a selected non-volatile memory cell in a memory array having a gate node coupled to a wordline WL(n) and a drain node connected to a selected bitline, comprising:
if a threshold voltage of the selected non-volatile memory cell is less than a target threshold voltage, then programming the selected non-volatile memory cell by,
holding the selected bitline at ground;
applying V dd to all unselected bitlines;
applying low passing voltage V passL , to a drain gate select (SGD) line;
applying V pp to common source line;
applying a high passing voltage V passH to all unselected wordlines except for the next neighbor word line WL(n−1);
applying the high passing voltage V passH to a source gate select (SGS) line;
applying V pgm to the selected word line WL(n); and
sweeping a next neighbor word line WL(n−1) gate node voltage from about 0 V to about a V read , wherein hot carriers from a drain region of an injecting memory cell having a gate node coupled to a next neighbor wordline WL(n−1) are injected into a floating gate of the selected non-volatile memory cell on the wordline WL(n).
11. A low voltage method of programming a non-volatile memory cell as recited in claim 10 , further comprising:
locking out the non-volatile memory cell if the threshold voltage is greater than the target threshold voltage.
12. A low voltage method as recited in claim 11 , further comprising:
incrementing the program voltage V pgm and the V passH and V passL voltages; and
continuing the programming of the non-volatile memory cell if the threshold voltage is less than the target threshold voltage, otherwise, locking out the non-volatile memory cell.
13. A low voltage method as recited in claim 12 , wherein V pgm ranges from about 8V to about 14V, V passL ranges from about 4V to about 10V, V passH ranges from about 5V to about 10V, V pp ranges from about 3.5V to about 5.5V, and V dd ranges from about 1.8V to about 3.6V.
14. A low voltage method of programming a selected non-volatile memory cell in a memory array having a gate node coupled to a wordline WL(n) and a drain node connected to a selected bitline, comprising:
if a threshold voltage of the selected non-volatile memory cell is less than a target threshold voltage, then programming the selected non-volatile memory cell by,
holding the selected bitline at V pp ;
grounding to all unselected bitlines;
applying high passing voltage V passH to SGD line and unselected wordlines except for the next neighbor wordline WL(n−1);
applying low passing voltage V passL to SGS line;
grounding common source line;
applying V pgm to the selected word line WL(n); and
sweeping a next neighbor word line WL(n−1) gate node voltage from about 0 V to about a V read , wherein hot carriers from a drain region of an injecting memory cell having a gate node coupled to a next neighbor wordline WL(n−1) are injected into a floating gate of the selected non-volatile memory cell on the wordline WL(n).
15. A low voltage method of programming a non-volatile memory cell as recited in claim 14 , further comprising:
locking out the non-volatile memory cell if the threshold voltage is greater than the target threshold voltage.
16. A low voltage method as recited in claim 15 , further comprising:
incrementing the program voltage V pgm and the V passH and V passL voltages; and
continuing the programming of the non-volatile memory cell if the threshold voltage is less than the target threshold voltage, otherwise, locking out the non-volatile memory cell.
17. A low voltage method as recited in claim 16 , wherein V pgm ranges from about 8V to about 14V, V passL ranges from about 4V to about 10V, V passH ranges from about 5V to about 10V, V pp ranges from about 3.5V to about 5.5V, and V dd ranges from about 1.8V to about 3.6V.