Level shifter circuit with stress test function

1. A level shifter circuit, wherein a circuit which turns on when a first reference potential is input as a control potential is used as a first-type MOS transistor, and a circuit which turns on when a second reference potential different from the first reference potential is input, is used as a second-type MOS transistor, the level shifter circuit comprising:

a first reference potential supply line to which a first reference potential is applied;

a second reference potential supply line to which a second reference potential different from the first reference potential is applied;

a first output potential supply circuit including a first first-type MOS transistor and a first second-type MOS transistor connected sequentially in series from the second reference potential supply line side, the first output potential supply circuit being connected between the first reference potential supply line and the second reference potential supply line;

a second output potential supply circuit including a second first-type MOS transistor and a second second-type MOS transistor connected sequentially in series from the second reference potential supply line side, the second output potential supply circuit being connected between the first reference potential supply line and the second reference potential supply line, the second output potential supply circuit being connected in parallel with the first output potential supply circuit between the first reference potential supply line and the second reference potential supply line;

a first connection line which supplies a potential between the second first-type MOS transistor and the second second-type MOS transistor to a control terminal of the first first-type MOS transistor;

a second connection line which supplies a potential between the first first-type MOS transistor and the first second-type MOS transistor to a control terminal of the second first-type MOS transistor;

a first input line which supplies a first input signal to a control terminal of the first second-type MOS transistor;

a second input line which supplies a second input signal to a control terminal of the second second-type MOS transistor;

a first output line which outputs a potential between the first first-type MOS transistor and the first second-type MOS transistor as a first output signal;

a second output line which outputs a potential between the second first-type MOS transistor and the second second-type MOS transistor as a second output signal; and

a stress test circuit which changes over the first output signal and the second output signal output to a controlled circuit from the first output line and the second output line, to any of signals when the controlled circuit is operating normally and signals when the controlled circuit is subjected to a stress test;

wherein the stress test circuit functions to:

during normal operation, when the first input signal and the second input signal having respectively different potentials are input to the first input line and the second input line, output the first output signal and the second output signal having respectively difference potentials for the first output line and the second output line, and

during the stress test, when the first input signal and the second input signal having respectively different potentials are input to the first input line and the second input line, output the first output signal and the second output signal having identical potentials from the first output line and the second output line;

wherein the stress test circuit includes:

a third first-type MOS transistor connected in series between the first first-type MOS transistor and the first second-type MOS transistor;

a fourth first-type MOS transistor connected in series between the second first-type MOS transistor and the second second-type MOS transistor; and

a drive control circuit which controls the first second-type MOS transistor, the second second-type MOS transistor, the third first-type MOS transistor and the fourth first-type MOS transistor;

wherein the drive control circuit:

during normal operation, switches both the third first-type MOS transistor and the fourth first-type MOS transistor ON, and switches one of the first second-type MOS transistor and the second second-type MOS transistor ON and the other OFF; and

during a stress test, switches both of the third first-type MOS transistor and the fourth first-type MOS transistor OFF, and both of the first second-type MOS transistor and the second second-type MOS transistor ON.

2. The level shifter circuit according to claim 1 , wherein:

the first reference potential is a ground potential;

the second reference potential is a potential higher than the ground potential;

the first-type MOS transistor is a P-channel transistor; and

the second-type MOS transistor is an N-channel transistor.